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radeon/llvm: Enable vec4 loads on R600

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This commit is contained in:
Tom Stellard 2012-06-28 20:27:55 +00:00
parent e17c586d08
commit a31b2f7107
3 changed files with 20 additions and 0 deletions
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3
src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
View file

@ -34,6 +34,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
setOperationAction(ISD::FRINT, MVT::f32, Legal);
setOperationAction(ISD::LOAD, MVT::f32, Custom);
setOperationAction(ISD::LOAD, MVT::v4f32, Custom);
setOperationAction(ISD::UDIV, MVT::i32, Expand);
setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
@ -139,6 +140,8 @@ SDValue AMDGPUTargetLowering::BitcastLOAD(SDValue Op, SelectionDAG &DAG) const
if (VT == MVT::f32) {
IntVT = MVT::i32;
} else if (VT == MVT::v4f32) {
IntVT = MVT::v4i32;
} else {
return Op;
}

1
src/gallium/drivers/radeon/R600CodeEmitter.cpp
View file

@ -205,6 +205,7 @@ bool R600CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
}
case AMDIL::VTX_READ_PARAM_eg:
case AMDIL::VTX_READ_GLOBAL_eg:
case AMDIL::VTX_READ_GLOBAL_128_eg:
{
uint64_t InstWord01 = getBinaryCodeForInstr(MI);
uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset

16
src/gallium/drivers/radeon/R600Instructions.td
View file

@ -1029,6 +1029,21 @@ def VTX_READ_GLOBAL_eg : VTX_READ_32_eg <1,
[(set (i32 R600_TReg32_X:$dst), (global_load ADDRVTX_READ:$ptr))]
>;
class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
: VTX_READ_eg <buffer_id, (outs R600_Reg128:$dst), pattern> {
let MEGA_FETCH_COUNT = 16;
let DST_SEL_X = 0;
let DST_SEL_Y = 1;
let DST_SEL_Z = 2;
let DST_SEL_W = 3;
let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
}
def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1,
[(set (v4i32 R600_Reg128:$dst), (global_load ADDRVTX_READ:$ptr))]
>;
}
let Predicates = [isCayman] in {
@ -1280,5 +1295,6 @@ def : Vector_Build <v4i32, R600_Reg32>;
def : BitConvert <i32, f32, R600_Reg32>;
def : BitConvert <f32, i32, R600_Reg32>;
def : BitConvert <v4f32, v4i32, R600_Reg128>;
} // End isR600toCayman Predicate