diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 1361f7f1d12..a55f96a1e68 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -135,6 +135,7 @@ const struct radv_dynamic_state default_dynamic_state = { .depth_clamp_enable = 0u, .color_write_mask = 0u, .color_blend_enable = 0u, + .rasterization_samples = VK_SAMPLE_COUNT_1_BIT, }; static void @@ -294,6 +295,8 @@ radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer, const struct radv_dy RADV_CMP_COPY(color_blend_enable, RADV_DYNAMIC_COLOR_BLEND_ENABLE); + RADV_CMP_COPY(rasterization_samples, RADV_DYNAMIC_RASTERIZATION_SAMPLES); + #undef RADV_CMP_COPY cmd_buffer->state.dirty |= dest_mask; @@ -954,6 +957,37 @@ radv_emit_descriptor_pointers(struct radv_device *device, struct radeon_cmdbuf * } } +static ALWAYS_INLINE unsigned +radv_get_rasterization_samples(struct radv_cmd_buffer *cmd_buffer) +{ + const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; + const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; + + if (pipeline->uses_bresenham_lines) { + return 1; + } + + return MAX2(1, d->rasterization_samples); +} + +static ALWAYS_INLINE unsigned +radv_get_ps_iter_samples(struct radv_cmd_buffer *cmd_buffer) +{ + const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; + const struct radv_rendering_state *render = &cmd_buffer->state.render; + unsigned ps_iter_samples = 1; + + if (pipeline->ms.sample_shading_enable) { + unsigned rasterization_samples = radv_get_rasterization_samples(cmd_buffer); + unsigned color_samples = MAX2(render->color_samples, rasterization_samples); + + ps_iter_samples = ceilf(pipeline->ms.min_sample_shading * color_samples); + ps_iter_samples = util_next_power_of_two(ps_iter_samples); + } + + return ps_iter_samples; +} + /** * Convert the user sample locations to hardware sample locations (the values * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*). @@ -1052,13 +1086,10 @@ static void radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer) { const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; - const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; uint32_t num_samples = (uint32_t)d->sample_location.per_pixel; - unsigned pa_sc_aa_config = pipeline->ms.pa_sc_aa_config; struct radeon_cmdbuf *cs = cmd_buffer->cs; uint32_t sample_locs_pixel[4][2] = {0}; VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */ - uint32_t max_sample_dist = 0; uint64_t centroid_priority; if (!d->sample_location.count) @@ -1078,14 +1109,6 @@ radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer) /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */ centroid_priority = radv_compute_centroid_priority(cmd_buffer, sample_locs[0], num_samples); - /* Compute the maximum sample distance from the specified locations. */ - for (unsigned i = 0; i < 4; ++i) { - for (uint32_t j = 0; j < num_samples; j++) { - VkOffset2D offset = sample_locs[i][j]; - max_sample_dist = MAX2(max_sample_dist, MAX2(abs(offset.x), abs(offset.y))); - } - } - /* Emit the specified user sample locations. */ switch (num_samples) { case 2: @@ -1121,12 +1144,6 @@ radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer) unreachable("invalid number of samples"); } - /* Emit the maximum sample distance and the centroid priority. */ - pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST; - pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist); - - radeon_set_context_reg(cs, R_028BE0_PA_SC_AA_CONFIG, pa_sc_aa_config); - radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2); radeon_emit(cs, centroid_priority); radeon_emit(cs, centroid_priority >> 32); @@ -1150,21 +1167,6 @@ radv_emit_inline_push_consts(struct radv_device *device, struct radeon_cmdbuf *c radeon_emit_array(cs, values, loc->num_sgprs); } -static void -radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer, - struct radv_graphics_pipeline *pipeline) -{ - int num_samples = pipeline->ms.num_samples; - struct radv_graphics_pipeline *old_pipeline = cmd_buffer->state.emitted_graphics_pipeline; - - if (old_pipeline && num_samples == old_pipeline->ms.num_samples) - return; - - radv_emit_default_sample_locations(cmd_buffer->cs, num_samples); - - cmd_buffer->state.context_roll_without_scissor_emitted = true; -} - struct radv_bin_size_entry { unsigned bpp; VkExtent2D extent; @@ -1195,8 +1197,7 @@ radv_gfx10_compute_bin_size(struct radv_graphics_pipeline *pipeline, const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count; - const unsigned total_samples = - 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->ms.pa_sc_aa_config); + const unsigned total_samples = radv_get_rasterization_samples(cmd_buffer); const unsigned samples_log = util_logbase2_ceil(total_samples); unsigned color_bytes_per_pixel = 0; @@ -1483,8 +1484,8 @@ radv_gfx9_compute_bin_size(struct radv_graphics_pipeline *pipeline, util_logbase2_ceil(pdevice->rad_info.max_render_backends / pdevice->rad_info.max_se); unsigned log_num_se = util_logbase2_ceil(pdevice->rad_info.max_se); - unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->ms.pa_sc_aa_config); - unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->ms.db_eqaa); + unsigned total_samples = radv_get_rasterization_samples(cmd_buffer); + unsigned ps_iter_samples = radv_get_ps_iter_samples(cmd_buffer); unsigned effective_samples = total_samples; unsigned color_bytes_per_pixel = 0; @@ -1881,8 +1882,6 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer) if (cmd_buffer->state.emitted_graphics_pipeline == pipeline) return; - radv_update_multisample_state(cmd_buffer, pipeline); - cmd_buffer->scratch_size_per_wave_needed = MAX2(cmd_buffer->scratch_size_per_wave_needed, pipeline->base.scratch_bytes_per_wave); cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted, pipeline->base.max_waves); @@ -1910,7 +1909,9 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer) RADV_CMD_DIRTY_DYNAMIC_PROVOKING_VERTEX_MODE | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT | RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLAMP_ENABLE | - RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE; + RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE | + RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE_ENABLE | + RADV_CMD_DIRTY_DYNAMIC_CONSERVATIVE_RAST_MODE; if (!cmd_buffer->state.emitted_graphics_pipeline || radv_rast_prim_is_points_or_lines(cmd_buffer->state.emitted_graphics_pipeline->rast_prim) != radv_rast_prim_is_points_or_lines(pipeline->rast_prim)) @@ -1926,15 +1927,6 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer) cmd_buffer->state.emitted_graphics_pipeline->vgt_tf_param != pipeline->vgt_tf_param) cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_TESS_DOMAIN_ORIGIN; - if (!cmd_buffer->state.emitted_graphics_pipeline || - cmd_buffer->state.emitted_graphics_pipeline->ms.pa_sc_mode_cntl_0 != pipeline->ms.pa_sc_mode_cntl_0) - cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE_ENABLE; - - if (!cmd_buffer->state.emitted_graphics_pipeline || - cmd_buffer->state.emitted_graphics_pipeline->ms.pa_sc_aa_config != pipeline->ms.pa_sc_aa_config || - cmd_buffer->state.emitted_graphics_pipeline->ms.db_eqaa != pipeline->ms.db_eqaa) - cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_CONSERVATIVE_RAST_MODE; - if (!cmd_buffer->state.emitted_graphics_pipeline || memcmp(cmd_buffer->state.emitted_graphics_pipeline->cb_blend_control, pipeline->cb_blend_control, sizeof(pipeline->cb_blend_control)) || @@ -1942,6 +1934,14 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer) pipeline->sx_mrt_blend_opt, sizeof(pipeline->sx_mrt_blend_opt))) cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_ENABLE; + if (!cmd_buffer->state.emitted_graphics_pipeline || + cmd_buffer->state.emitted_graphics_pipeline->ms.sample_shading_enable != pipeline->ms.sample_shading_enable || + cmd_buffer->state.emitted_graphics_pipeline->ms.min_sample_shading != pipeline->ms.min_sample_shading || + cmd_buffer->state.emitted_graphics_pipeline->uses_bresenham_lines != pipeline->uses_bresenham_lines || + cmd_buffer->state.emitted_graphics_pipeline->pa_sc_mode_cntl_1 != pipeline->pa_sc_mode_cntl_1 || + cmd_buffer->state.emitted_graphics_pipeline->db_render_control != pipeline->db_render_control) + cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES; + radeon_emit_array(cmd_buffer->cs, pipeline->base.cs.buf, pipeline->base.cs.cdw); if (pipeline->has_ngg_culling && @@ -2479,10 +2479,7 @@ static void radv_emit_conservative_rast_mode(struct radv_cmd_buffer *cmd_buffer) { const struct radv_physical_device *pdevice = cmd_buffer->device->physical_device; - const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; - unsigned pa_sc_aa_config = pipeline->ms.pa_sc_aa_config; - unsigned db_eqaa = pipeline->ms.db_eqaa; if (pdevice->rad_info.gfx_level >= GFX9) { uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1); @@ -2503,19 +2500,11 @@ radv_emit_conservative_rast_mode(struct radv_cmd_buffer *cmd_buffer) S_028C4C_UNDER_RAST_ENABLE(1) | S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) | S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0); } - - /* Adjust MSAA state if conservative rasterization is enabled. */ - pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1); - db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) | - S_028804_OVERRASTERIZATION_AMOUNT(4); } radeon_set_context_reg(cmd_buffer->cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, pa_sc_conservative_rast); } - - radeon_set_context_reg(cmd_buffer->cs, R_028BE0_PA_SC_AA_CONFIG, pa_sc_aa_config); - radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, db_eqaa); } static void @@ -2529,6 +2518,83 @@ radv_emit_depth_clamp_enable(struct radv_cmd_buffer *cmd_buffer) S_02800C_DISABLE_VIEWPORT_CLAMP(mode == RADV_DEPTH_CLAMP_MODE_DISABLED)); } +static unsigned +radv_get_pa_sc_mode_cntl_1(struct radv_cmd_buffer *cmd_buffer) +{ + const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; + unsigned rasterization_samples = radv_get_rasterization_samples(cmd_buffer); + unsigned pa_sc_mode_cntl_1 = pipeline->pa_sc_mode_cntl_1; + + if (rasterization_samples) { + unsigned ps_iter_samples = radv_get_ps_iter_samples(cmd_buffer); + + pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1); + } + + return pa_sc_mode_cntl_1; +} + +static void +radv_emit_rasterization_samples(struct radv_cmd_buffer *cmd_buffer) +{ + const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; + const struct radv_physical_device *pdevice = pipeline->base.device->physical_device; + unsigned rasterization_samples = radv_get_rasterization_samples(cmd_buffer); + const struct radv_rendering_state *render = &cmd_buffer->state.render; + unsigned pa_sc_mode_cntl_1 = radv_get_pa_sc_mode_cntl_1(cmd_buffer); + const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; + unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1); + unsigned db_render_control = pipeline->db_render_control; + + if (!d->sample_location.count) + radv_emit_default_sample_locations(cmd_buffer->cs, rasterization_samples); + + if (rasterization_samples > 1) { + unsigned ps_iter_samples = radv_get_ps_iter_samples(cmd_buffer); + + if (ps_iter_samples > 1) + spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2); + } + + if (pdevice->rad_info.gfx_level >= GFX11) { + unsigned num_samples = render->max_samples; + unsigned max_allowed_tiles_in_wave = 0; + + if (pdevice->rad_info.has_dedicated_vram) { + if (num_samples == 8) + max_allowed_tiles_in_wave = 7; + else if (num_samples == 4) + max_allowed_tiles_in_wave = 14; + } else { + if (num_samples == 8) + max_allowed_tiles_in_wave = 8; + } + + /* TODO: We may want to disable this workaround for future chips. */ + if (num_samples >= 4) { + if (max_allowed_tiles_in_wave) + max_allowed_tiles_in_wave--; + else + max_allowed_tiles_in_wave = 15; + } + + db_render_control |= S_028000_OREO_MODE(V_028000_OMODE_O_THEN_B) | + S_028000_MAX_ALLOWED_TILES_IN_WAVE(max_allowed_tiles_in_wave); + } + + radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, db_render_control); + radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl); + radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, pa_sc_mode_cntl_1); + + /* Pass the number of samples to the fragment shader because it might be needed. */ + struct radv_userdata_info *loc = + radv_lookup_user_sgpr(&pipeline->base, MESA_SHADER_FRAGMENT, AC_UD_PS_NUM_SAMPLES); + if (loc->sgpr_idx != -1) { + uint32_t base_reg = pipeline->base.user_data_0[MESA_SHADER_FRAGMENT]; + radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, rasterization_samples); + } +} + static void radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index, struct radv_color_buffer_info *cb, struct radv_image_view *iview, @@ -3477,7 +3543,7 @@ radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer, bool enable_occlus { bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled; struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; - uint32_t pa_sc_mode_cntl_1 = pipeline ? pipeline->ms.pa_sc_mode_cntl_1 : 0; + uint32_t pa_sc_mode_cntl_1 = pipeline ? radv_get_pa_sc_mode_cntl_1(cmd_buffer) : 0; uint32_t db_count_control; if (!enable_occlusion_queries) { @@ -3908,18 +3974,6 @@ radv_emit_tess_domain_origin(struct radv_cmd_buffer *cmd_buffer) radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM, vgt_tf_param); } -static void -radv_emit_line_stipple_enable(struct radv_cmd_buffer *cmd_buffer) -{ - const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; - const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; - unsigned pa_sc_mode_cntl_0 = pipeline->ms.pa_sc_mode_cntl_0; - - pa_sc_mode_cntl_0 |= S_028A48_LINE_STIPPLE_ENABLE(d->stippled_line_enable); - - radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, pa_sc_mode_cntl_0); -} - static void radv_emit_alpha_to_coverage_enable(struct radv_cmd_buffer *cmd_buffer) { @@ -3988,6 +4042,75 @@ radv_emit_color_blend_enable(struct radv_cmd_buffer *cmd_buffer) } } +static void +radv_emit_msaa_state(struct radv_cmd_buffer *cmd_buffer) +{ + const struct radv_physical_device *pdevice = cmd_buffer->device->physical_device; + unsigned rasterization_samples = radv_get_rasterization_samples(cmd_buffer); + const struct radv_rendering_state *render = &cmd_buffer->state.render; + const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; + unsigned log_samples = util_logbase2(rasterization_samples); + unsigned pa_sc_aa_config = 0; + unsigned max_sample_dist = 0; + unsigned db_eqaa; + + db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) | S_028804_INCOHERENT_EQAA_READS(1) | + S_028804_INTERPOLATE_COMP_Z(1) | S_028804_STATIC_ANCHOR_ASSOCIATIONS(1); + + if (pdevice->rad_info.gfx_level >= GFX9 && + d->conservative_rast_mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) { + /* Adjust MSAA state if conservative rasterization is enabled. */ + db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) | S_028804_OVERRASTERIZATION_AMOUNT(4); + pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1); + } + + if (!d->sample_location.count) { + max_sample_dist = radv_get_default_max_sample_dist(log_samples); + } else { + uint32_t num_samples = (uint32_t)d->sample_location.per_pixel; + VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */ + + /* Convert the user sample locations to hardware sample locations. */ + radv_convert_user_sample_locs(&d->sample_location, 0, 0, sample_locs[0]); + radv_convert_user_sample_locs(&d->sample_location, 1, 0, sample_locs[1]); + radv_convert_user_sample_locs(&d->sample_location, 0, 1, sample_locs[2]); + radv_convert_user_sample_locs(&d->sample_location, 1, 1, sample_locs[3]); + + /* Compute the maximum sample distance from the specified locations. */ + for (unsigned i = 0; i < 4; ++i) { + for (uint32_t j = 0; j < num_samples; j++) { + VkOffset2D offset = sample_locs[i][j]; + max_sample_dist = MAX2(max_sample_dist, MAX2(abs(offset.x), abs(offset.y))); + } + } + } + + if (rasterization_samples > 1) { + unsigned z_samples = MAX2(render->ds_samples, rasterization_samples); + unsigned ps_iter_samples = radv_get_ps_iter_samples(cmd_buffer); + unsigned log_z_samples = util_logbase2(z_samples); + unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples); + + db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) | + S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) | + S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) | + S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples); + + pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) | + S_028BE0_MAX_SAMPLE_DIST(max_sample_dist) | + S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | /* CM_R_028BE0_PA_SC_AA_CONFIG */ + S_028BE0_COVERED_CENTROID_IS_CENTER(pdevice->rad_info.gfx_level >= GFX10_3); + } + + radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, db_eqaa); + radeon_set_context_reg(cmd_buffer->cs, R_028BE0_PA_SC_AA_CONFIG, pa_sc_aa_config); + radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, + S_028A48_ALTERNATE_RBS_PER_TILE(pdevice->rad_info.gfx_level >= GFX9) | + S_028A48_VPORT_SCISSOR_ENABLE(1) | + S_028A48_LINE_STIPPLE_ENABLE(d->stippled_line_enable) | + S_028A48_MSAA_ENABLE(rasterization_samples > 1)); +} + static void radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty) { @@ -4082,9 +4205,6 @@ radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer, bool pip if (states & RADV_CMD_DIRTY_DYNAMIC_TESS_DOMAIN_ORIGIN) radv_emit_tess_domain_origin(cmd_buffer); - if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE_ENABLE) - radv_emit_line_stipple_enable(cmd_buffer); - if (states & RADV_CMD_DIRTY_DYNAMIC_ALPHA_TO_COVERAGE_ENABLE) radv_emit_alpha_to_coverage_enable(cmd_buffer); @@ -4098,6 +4218,15 @@ radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer, bool pip if (states & RADV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_ENABLE) radv_emit_color_blend_enable(cmd_buffer); + if (states & RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES) + radv_emit_rasterization_samples(cmd_buffer); + + if (states & (RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE_ENABLE | + RADV_CMD_DIRTY_DYNAMIC_CONSERVATIVE_RAST_MODE | + RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS | + RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES)) + radv_emit_msaa_state(cmd_buffer); + cmd_buffer->state.dirty &= ~states; } @@ -6021,11 +6150,17 @@ radv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipeline } } + /* Re-emit the rasterization samples state because the SGPR idx can be different. */ + const struct radv_shader *ps = graphics_pipeline->base.shaders[MESA_SHADER_FRAGMENT]; + if (ps->info.user_sgprs_locs.shader_data[AC_UD_PS_NUM_SAMPLES].sgpr_idx != -1) { + cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES; + } + radv_bind_dynamic_state(cmd_buffer, &graphics_pipeline->dynamic_state); radv_bind_vs_input_state(cmd_buffer, graphics_pipeline); - if (graphics_pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions) + if (ps->info.ps.needs_sample_positions) cmd_buffer->sample_positions_needed = true; if (graphics_pipeline->esgs_ring_size > cmd_buffer->esgs_ring_size_needed) @@ -6721,6 +6856,18 @@ radv_CmdSetColorBlendEnableEXT(VkCommandBuffer commandBuffer, uint32_t firstAtta state->dirty |= RADV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_ENABLE; } +VKAPI_ATTR void VKAPI_CALL +radv_CmdSetRasterizationSamplesEXT(VkCommandBuffer commandBuffer, + VkSampleCountFlagBits rasterizationSamples) +{ + RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); + struct radv_cmd_state *state = &cmd_buffer->state; + + state->dynamic.rasterization_samples = rasterizationSamples; + + state->dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES; +} + VKAPI_ATTR void VKAPI_CALL radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCount, const VkCommandBuffer *pCmdBuffers) @@ -8127,8 +8274,9 @@ radv_get_ngg_culling_settings(struct radv_cmd_buffer *cmd_buffer, bool vp_y_inve * num_samples is also always a power of two, so the small prim precision can only be * a power of two between 2^-2 and 2^-6, therefore it's enough to remember the exponent. */ + unsigned rasterization_samples = radv_get_rasterization_samples(cmd_buffer); unsigned subpixel_bits = 256; - int32_t small_prim_precision_log2 = util_logbase2(pipeline->ms.num_samples) - util_logbase2(subpixel_bits); + int32_t small_prim_precision_log2 = util_logbase2(rasterization_samples) - util_logbase2(subpixel_bits); nggc_settings |= ((uint32_t) small_prim_precision_log2 << 24u); } @@ -8159,7 +8307,7 @@ radv_emit_ngg_culling_state(struct radv_cmd_buffer *cmd_buffer, const struct rad (RADV_CMD_DIRTY_PIPELINE | RADV_CMD_DIRTY_DYNAMIC_CULL_MODE | RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE | RADV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT | - RADV_CMD_DIRTY_DYNAMIC_CONSERVATIVE_RAST_MODE); + RADV_CMD_DIRTY_DYNAMIC_CONSERVATIVE_RAST_MODE | RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES); /* Check small draw status: * For small draw calls, we disable culling by setting the SGPR to 0. @@ -8205,8 +8353,8 @@ radv_emit_ngg_culling_state(struct radv_cmd_buffer *cmd_buffer, const struct rad /* Correction for number of samples per pixel. */ for (unsigned i = 0; i < 2; ++i) { - vp_scale[i] *= (float) pipeline->ms.num_samples; - vp_translate[i] *= (float) pipeline->ms.num_samples; + vp_scale[i] *= (float) cmd_buffer->state.dynamic.rasterization_samples; + vp_translate[i] *= (float) cmd_buffer->state.dynamic.rasterization_samples; } uint32_t vp_reg_values[4] = {fui(vp_scale[0]), fui(vp_scale[1]), fui(vp_translate[0]), fui(vp_translate[1])}; @@ -8268,7 +8416,8 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r cmd_buffer->state.graphics_pipeline->is_ngg) radv_emit_ngg_culling_state(cmd_buffer, info); - if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_MASK) || + if ((cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_MASK | + RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES)) || cmd_buffer->state.emitted_graphics_pipeline != cmd_buffer->state.graphics_pipeline) radv_emit_binning_state(cmd_buffer, cmd_buffer->state.graphics_pipeline); diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index dfc07f5df4a..7abb46e9ace 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -69,7 +69,6 @@ struct radv_blend_state { }; struct radv_depth_stencil_state { - uint32_t db_render_control; uint32_t db_shader_control; }; @@ -873,35 +872,6 @@ radv_pipeline_init_blend_state(struct radv_graphics_pipeline *pipeline, return blend; } -static unsigned -radv_pipeline_color_samples(const struct vk_graphics_pipeline_state *state) -{ - if (radv_pipeline_has_color_attachments(state->rp)) { - unsigned color_attachment_samples = 0; - for (uint32_t i = 0; i < state->rp->color_attachment_count; i++) { - if (state->rp->color_attachment_formats[i] != VK_FORMAT_UNDEFINED) { - color_attachment_samples = - MAX2(color_attachment_samples, state->rp->color_attachment_samples[i]); - } - } - - if (color_attachment_samples) - return color_attachment_samples; - } - - return state->ms ? state->ms->rasterization_samples : 1; -} - -static unsigned -radv_pipeline_depth_samples(const struct vk_graphics_pipeline_state *state) -{ - if (state->rp->depth_stencil_attachment_samples && radv_pipeline_has_ds_attachments(state->rp)) { - return state->rp->depth_stencil_attachment_samples; - } - - return state->ms ? state->ms->rasterization_samples : 1; -} - static bool radv_is_depth_write_enabled(const struct vk_depth_stencil_state *ds) { @@ -1070,9 +1040,6 @@ radv_pipeline_init_multisample_state(struct radv_graphics_pipeline *pipeline, struct radv_multisample_state *ms = &pipeline->ms; unsigned num_tile_pipes = pdevice->rad_info.num_tile_pipes; bool out_of_order_rast = false; - int ps_iter_samples = 1; - - ms->num_samples = state->ms ? state->ms->rasterization_samples : 1; /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading: * @@ -1092,17 +1059,13 @@ radv_pipeline_init_multisample_state(struct radv_graphics_pipeline *pipeline, */ if (pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.ps.uses_sample_shading || (state->ms && state->ms->sample_shading_enable)) { - uint32_t color_samples = radv_pipeline_color_samples(state); - float min_sample_shading; - if (pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.ps.uses_sample_shading) { - min_sample_shading = 1.0f; + ms->min_sample_shading = 1.0f; } else { - min_sample_shading = state->ms->min_sample_shading; + ms->min_sample_shading = state->ms->min_sample_shading; } - ps_iter_samples = ceilf(min_sample_shading * color_samples); - ps_iter_samples = util_next_power_of_two(ps_iter_samples); + ms->sample_shading_enable = true; } if (state->rs->rasterization_order_amd == VK_RASTERIZATION_ORDER_RELAXED_AMD) { @@ -1117,12 +1080,7 @@ radv_pipeline_init_multisample_state(struct radv_graphics_pipeline *pipeline, out_of_order_rast = radv_pipeline_out_of_order_rast(pipeline, blend, state); } - ms->pa_sc_aa_config = 0; - ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) | S_028804_INCOHERENT_EQAA_READS(1) | - S_028804_INTERPOLATE_COMP_Z(pdevice->rad_info.gfx_level < GFX11) | - S_028804_STATIC_ANCHOR_ASSOCIATIONS(1); - - ms->pa_sc_mode_cntl_1 = + pipeline->pa_sc_mode_cntl_1 = S_028A4C_WALK_FENCE_ENABLE(1) | // TODO linear dst fixes S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) | S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) | @@ -1131,8 +1089,6 @@ radv_pipeline_init_multisample_state(struct radv_graphics_pipeline *pipeline, S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) | S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) | S_028A4C_TILE_WALK_ORDER_ENABLE(1) | S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) | S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | S_028A4C_FORCE_EOV_REZ_ENABLE(1); - ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pdevice->rad_info.gfx_level >= GFX9) | - S_028A48_VPORT_SCISSOR_ENABLE(1); if (state->rs->line.mode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT && radv_rast_prim_is_line(rast_prim)) { @@ -1145,27 +1101,7 @@ radv_pipeline_init_multisample_state(struct radv_graphics_pipeline *pipeline, * number of rasterization samples, and cover all samples in those pixels (unless masked out * or killed)." */ - ms->num_samples = 1; - } - - if (ms->num_samples > 1) { - uint32_t z_samples = radv_pipeline_depth_samples(state); - unsigned log_samples = util_logbase2(ms->num_samples); - unsigned log_z_samples = util_logbase2(z_samples); - unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples); - ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1); - ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) | - S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) | - S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) | - S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples); - ms->pa_sc_aa_config |= - S_028BE0_MSAA_NUM_SAMPLES(log_samples) | - S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) | - S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | /* CM_R_028BE0_PA_SC_AA_CONFIG */ - S_028BE0_COVERED_CENTROID_IS_CENTER(pdevice->rad_info.gfx_level >= GFX10_3); - ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1); - if (ps_iter_samples > 1) - pipeline->spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2); + pipeline->uses_bresenham_lines = true; } } @@ -1174,7 +1110,6 @@ gfx103_pipeline_init_vrs_state(struct radv_graphics_pipeline *pipeline, const struct vk_graphics_pipeline_state *state) { struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT]; - struct radv_multisample_state *ms = &pipeline->ms; struct radv_vrs_state *vrs = &pipeline->vrs; if ((state->ms && state->ms->sample_shading_enable) || @@ -1194,8 +1129,8 @@ gfx103_pipeline_init_vrs_state(struct radv_graphics_pipeline *pipeline, * mode if PS_ITER_SAMPLE is 0, and it uses the per-draw rate. * The default VRS rate when sample shading is enabled is 1x1. */ - if (!G_028A4C_PS_ITER_SAMPLE(ms->pa_sc_mode_cntl_1)) - ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(1); + if (!G_028A4C_PS_ITER_SAMPLE(pipeline->pa_sc_mode_cntl_1)) + pipeline->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(1); } else { vrs->pa_cl_vrs_cntl = S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_VRS_COMB_MODE_PASSTHRU); } @@ -1330,6 +1265,8 @@ radv_dynamic_state_mask(VkDynamicState state) return RADV_DYNAMIC_COLOR_WRITE_MASK; case VK_DYNAMIC_STATE_COLOR_BLEND_ENABLE_EXT: return RADV_DYNAMIC_COLOR_BLEND_ENABLE; + case VK_DYNAMIC_STATE_RASTERIZATION_SAMPLES_EXT: + return RADV_DYNAMIC_RASTERIZATION_SAMPLES; default: unreachable("Unhandled dynamic state"); } @@ -1927,6 +1864,10 @@ radv_pipeline_init_dynamic_state(struct radv_graphics_pipeline *pipeline, } } + if (states & RADV_DYNAMIC_RASTERIZATION_SAMPLES) { + dynamic->rasterization_samples = state->ms->rasterization_samples; + } + pipeline->dynamic_state.mask = states; } @@ -2000,38 +1941,10 @@ radv_pipeline_init_depth_stencil_state(struct radv_graphics_pipeline *pipeline, const struct vk_graphics_pipeline_state *state, const VkGraphicsPipelineCreateInfo *pCreateInfo) { - const struct radv_physical_device *pdevice = pipeline->base.device->physical_device; struct radv_depth_stencil_state ds_state = {0}; ds_state.db_shader_control = radv_compute_db_shader_control(pipeline, state, pCreateInfo); - if (pdevice->rad_info.gfx_level >= GFX11) { - unsigned max_allowed_tiles_in_wave = 0; - unsigned num_samples = MAX2(radv_pipeline_color_samples(state), - radv_pipeline_depth_samples(state)); - - if (pdevice->rad_info.has_dedicated_vram) { - if (num_samples == 8) - max_allowed_tiles_in_wave = 7; - else if (num_samples == 4) - max_allowed_tiles_in_wave = 14; - } else { - if (num_samples == 8) - max_allowed_tiles_in_wave = 8; - } - - /* TODO: We may want to disable this workaround for future chips. */ - if (num_samples >= 4) { - if (max_allowed_tiles_in_wave) - max_allowed_tiles_in_wave--; - else - max_allowed_tiles_in_wave = 15; - } - - ds_state.db_render_control |= S_028000_OREO_MODE(V_028000_OMODE_O_THEN_B) | - S_028000_MAX_ALLOWED_TILES_IN_WAVE(max_allowed_tiles_in_wave); - } - return ds_state; } @@ -2839,7 +2752,8 @@ radv_generate_graphics_pipeline_key(const struct radv_graphics_pipeline *pipelin if (state->ms) { key.ps.sample_shading_enable = state->ms->sample_shading_enable; - if (state->ms->rasterization_samples > 1) { + if (!(pipeline->dynamic_states & RADV_DYNAMIC_RASTERIZATION_SAMPLES) && + state->ms->rasterization_samples > 1) { key.ps.num_samples = state->ms->rasterization_samples; } } @@ -2897,7 +2811,8 @@ radv_generate_graphics_pipeline_key(const struct radv_graphics_pipeline *pipelin !!(pipeline->dynamic_states & RADV_DYNAMIC_PATCH_CONTROL_POINTS); key.dynamic_rasterization_samples = - !!(pipeline->active_stages & VK_SHADER_STAGE_FRAGMENT_BIT) && !state->ms; + !!(pipeline->dynamic_states & RADV_DYNAMIC_RASTERIZATION_SAMPLES) || + (!!(pipeline->active_stages & VK_SHADER_STAGE_FRAGMENT_BIT) && !state->ms); key.dynamic_color_write_mask = !!(pipeline->dynamic_states & RADV_DYNAMIC_COLOR_WRITE_MASK); @@ -4201,7 +4116,6 @@ static void radv_pipeline_emit_depth_stencil_state(struct radeon_cmdbuf *ctx_cs, const struct radv_depth_stencil_state *ds_state) { - radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, ds_state->db_render_control); radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL, ds_state->db_shader_control); } @@ -4215,15 +4129,6 @@ radv_pipeline_emit_blend_state(struct radeon_cmdbuf *ctx_cs, radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask); } -static void -radv_pipeline_emit_multisample_state(struct radeon_cmdbuf *ctx_cs, - const struct radv_graphics_pipeline *pipeline) -{ - const struct radv_multisample_state *ms = &pipeline->ms; - - radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1); -} - static void radv_pipeline_emit_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs, const struct radv_graphics_pipeline *pipeline) @@ -4893,19 +4798,10 @@ radv_pipeline_emit_fragment_shader(struct radeon_cmdbuf *ctx_cs, struct radeon_c S_0286D8_PS_W32_EN(ps->info.wave_size == 32) | S_0286D8_PARAM_GEN(param_gen)); - radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->spi_baryc_cntl); - radeon_set_context_reg( ctx_cs, R_028710_SPI_SHADER_Z_FORMAT, ac_get_spi_shader_z_format(ps->info.ps.writes_z, ps->info.ps.writes_stencil, ps->info.ps.writes_sample_mask, ps->info.ps.writes_mrt0_alpha)); - - struct radv_userdata_info *loc = - radv_lookup_user_sgpr(&pipeline->base, MESA_SHADER_FRAGMENT, AC_UD_PS_NUM_SAMPLES); - if (loc->sgpr_idx != -1) { - uint32_t base_reg = pipeline->base.user_data_0[MESA_SHADER_FRAGMENT]; - radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, pipeline->ms.num_samples); - } } static void @@ -5151,7 +5047,6 @@ radv_pipeline_emit_pm4(struct radv_graphics_pipeline *pipeline, radv_pipeline_emit_depth_stencil_state(ctx_cs, ds_state); radv_pipeline_emit_blend_state(ctx_cs, pipeline, blend); - radv_pipeline_emit_multisample_state(ctx_cs, pipeline); radv_pipeline_emit_vgt_gs_mode(ctx_cs, pipeline); radv_pipeline_emit_vertex_shader(ctx_cs, cs, pipeline); radv_pipeline_emit_mesh_shader(ctx_cs, cs, pipeline); @@ -5412,7 +5307,6 @@ static void radv_pipeline_init_extra(struct radv_graphics_pipeline *pipeline, const struct radv_graphics_pipeline_create_info *extra, struct radv_blend_state *blend_state, - struct radv_depth_stencil_state *ds_state, const struct vk_graphics_pipeline_state *state, uint32_t *vgt_gs_out_prim_type) { @@ -5444,11 +5338,11 @@ radv_pipeline_init_extra(struct radv_graphics_pipeline *pipeline, } if (radv_pipeline_has_ds_attachments(state->rp)) { - ds_state->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear); - ds_state->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear); - ds_state->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->resummarize_enable); - ds_state->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->depth_compress_disable); - ds_state->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->stencil_compress_disable); + pipeline->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear); + pipeline->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear); + pipeline->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->resummarize_enable); + pipeline->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->depth_compress_disable); + pipeline->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->stencil_compress_disable); } } @@ -5530,8 +5424,6 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv return result; } - pipeline->spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1); - uint32_t vgt_gs_out_prim_type = radv_pipeline_init_vgt_gs_out(pipeline, &state); radv_pipeline_init_multisample_state(pipeline, &blend, &state, vgt_gs_out_prim_type); @@ -5620,7 +5512,7 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv pipeline->base.dynamic_offset_count = pipeline_layout.dynamic_offset_count; if (extra) { - radv_pipeline_init_extra(pipeline, extra, &blend, &ds_state, &state, &vgt_gs_out_prim_type); + radv_pipeline_init_extra(pipeline, extra, &blend, &state, &vgt_gs_out_prim_type); } radv_pipeline_emit_pm4(pipeline, &blend, &ds_state, vgt_gs_out_prim_type, &state); diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 1eca6a3e12c..2d39e8110d3 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1136,7 +1136,8 @@ enum radv_dynamic_state_bits { RADV_DYNAMIC_DEPTH_CLAMP_ENABLE = 1ull << 40, RADV_DYNAMIC_COLOR_WRITE_MASK = 1ull << 41, RADV_DYNAMIC_COLOR_BLEND_ENABLE = 1ull << 42, - RADV_DYNAMIC_ALL = (1ull << 43) - 1, + RADV_DYNAMIC_RASTERIZATION_SAMPLES = 1ull << 43, + RADV_DYNAMIC_ALL = (1ull << 44) - 1, }; enum radv_cmd_dirty_bits { @@ -1185,13 +1186,14 @@ enum radv_cmd_dirty_bits { RADV_CMD_DIRTY_DYNAMIC_DEPTH_CLAMP_ENABLE = 1ull << 40, RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_MASK = 1ull << 41, RADV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_ENABLE = 1ull << 42, - RADV_CMD_DIRTY_DYNAMIC_ALL = (1ull << 43) - 1, - RADV_CMD_DIRTY_PIPELINE = 1ull << 43, - RADV_CMD_DIRTY_INDEX_BUFFER = 1ull << 44, - RADV_CMD_DIRTY_FRAMEBUFFER = 1ull << 45, - RADV_CMD_DIRTY_VERTEX_BUFFER = 1ull << 46, - RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1ull << 47, - RADV_CMD_DIRTY_GUARDBAND = 1ull << 48, + RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES = 1ull << 43, + RADV_CMD_DIRTY_DYNAMIC_ALL = (1ull << 44) - 1, + RADV_CMD_DIRTY_PIPELINE = 1ull << 44, + RADV_CMD_DIRTY_INDEX_BUFFER = 1ull << 45, + RADV_CMD_DIRTY_FRAMEBUFFER = 1ull << 46, + RADV_CMD_DIRTY_VERTEX_BUFFER = 1ull << 47, + RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1ull << 48, + RADV_CMD_DIRTY_GUARDBAND = 1ull << 49, }; enum radv_cmd_flush_bits { @@ -1415,6 +1417,8 @@ struct radv_dynamic_state { uint32_t color_write_mask; uint32_t color_blend_enable; + + VkSampleCountFlagBits rasterization_samples; }; extern const struct radv_dynamic_state default_dynamic_state; @@ -1983,11 +1987,8 @@ extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS]; unsigned radv_format_meta_fs_key(struct radv_device *device, VkFormat format); struct radv_multisample_state { - uint32_t db_eqaa; - uint32_t pa_sc_mode_cntl_0; - uint32_t pa_sc_mode_cntl_1; - uint32_t pa_sc_aa_config; - unsigned num_samples; + bool sample_shading_enable; + float min_sample_shading; }; struct radv_vrs_state { @@ -2098,7 +2099,6 @@ struct radv_graphics_pipeline { uint64_t dynamic_states; struct radv_multisample_state ms; struct radv_vrs_state vrs; - uint32_t spi_baryc_cntl; unsigned esgs_ring_size; unsigned gsvs_ring_size; uint32_t vtx_base_sgpr; @@ -2117,6 +2117,8 @@ struct radv_graphics_pipeline { uint32_t vb_desc_usage_mask; uint32_t vb_desc_alloc_size; uint32_t vgt_tf_param; + uint32_t pa_sc_mode_cntl_1; + uint32_t db_render_control; /* Last pre-PS API stage */ gl_shader_stage last_vgt_api_stage; @@ -2131,6 +2133,7 @@ struct radv_graphics_pipeline { bool use_per_attribute_vb_descs; bool can_use_simple_input; bool uses_user_sample_locations; + bool uses_bresenham_lines; /* Whether the pipeline forces per-vertex VRS (GFX10.3+). */ bool force_vrs_per_vertex;