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i965: Emit a CS stall before timestamp writes.

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This implements one of the Sandybridge PIPE_CONTROL workarounds.  It
doesn't appear to be required for Ivybridge.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Kenneth Graunke 2012-08-07 09:32:46 -07:00
parent c4c78c275a
commit a2cdd5ada8
1 changed files with 14 additions and 0 deletions
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14
src/mesa/drivers/dri/i965/brw_queryobj.c
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@ -49,6 +49,20 @@ static void
write_timestamp(struct intel_context *intel, drm_intel_bo *query_bo, int idx)
{
if (intel->gen >= 6) {
/* Emit workaround flushes: */
if (intel->gen == 6) {
/* The timestamp write below is a non-zero post-sync op, which on
* Gen6 necessitates a CS stall. CS stalls need stall at scoreboard
* set. See the comments for intel_emit_post_sync_nonzero_flush().
*/
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
OUT_BATCH(PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD);
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
}
BEGIN_BATCH(5);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
OUT_BATCH(PIPE_CONTROL_WRITE_TIMESTAMP);