From a23fc3f066d6acf0f1efdf3116dfa0c6fda9e86b Mon Sep 17 00:00:00 2001 From: Georg Lehmann Date: Thu, 4 Jun 2026 13:54:01 +0200 Subject: [PATCH] radv/gfx12: program SPI_SHADER_PGM_RSRC4_GS for seperately compiled gs Cc: mesa-stable Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 34158a6e3af..2a9bb579e62 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -3033,7 +3033,6 @@ radv_emit_hw_ngg(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *e gfx12_push_sh_reg(shader->regs.pgm_lo, va >> 8); gfx12_push_sh_reg(shader->regs.pgm_rsrc1, shader->config.rsrc1); gfx12_push_sh_reg(shader->regs.pgm_rsrc2, shader->config.rsrc2); - gfx12_push_sh_reg(R_00B220_SPI_SHADER_PGM_RSRC4_GS, shader->regs.spi_shader_pgm_rsrc4_gs); } else { radeon_set_sh_reg(shader->regs.pgm_lo, va >> 8); radeon_set_sh_reg_seq(shader->regs.pgm_rsrc1, 2); @@ -3139,6 +3138,9 @@ radv_emit_hw_ngg(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *e if (pdev->info.gfx_level >= GFX12) { radeon_set_uconfig_reg(R_030988_VGT_PRIMITIVEID_EN, shader->regs.ngg.vgt_primitiveid_en); + + gfx12_push_sh_reg(R_00B220_SPI_SHADER_PGM_RSRC4_GS, shader->regs.spi_shader_pgm_rsrc4_gs); + gfx12_push_sh_reg(ngg_lds_layout_offset, SET_SGPR_FIELD(NGG_LDS_LAYOUT_GS_OUT_VERTEX_BASE, shader->info.ngg_info.esgs_ring_size)); } else {