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freedreno: small bit of cleanup about max rendertargets

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We hard-coded 4 or 8 as the max in various places.  Switch it all to a
define since the limit will go up with a4xx (and maybe even again in the
future?)

Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark 2015-07-31 09:36:31 -04:00
parent 5f247a9656
commit a221f8d9eb
13 changed files with 40 additions and 17 deletions
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4
src/gallium/drivers/freedreno/a3xx/fd3_blend.h
View file

@ -32,6 +32,8 @@
#include "pipe/p_state.h"
#include "pipe/p_context.h"
#include "freedreno_util.h"
struct fd3_blend_stateobj {
struct pipe_blend_state base;
struct {
@ -42,7 +44,7 @@ struct fd3_blend_stateobj {
/* Blend control bits for alpha channel */
uint32_t blend_control_alpha;
uint32_t control;
} rb_mrt[4];
} rb_mrt[A3XX_MAX_RENDER_TARGETS];
};
static inline struct fd3_blend_stateobj *

2
src/gallium/drivers/freedreno/a3xx/fd3_draw.c
View file

@ -324,7 +324,7 @@ fd3_clear(struct fd_context *ctx, unsigned buffers,
A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
}
for (i = 0; i < 4; i++) {
for (i = 0; i < A3XX_MAX_RENDER_TARGETS; i++) {
OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_ALWAYS) |

2
src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
View file

@ -57,7 +57,7 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
tile_mode = LINEAR;
}
for (i = 0; i < 4; i++) {
for (i = 0; i < A3XX_MAX_RENDER_TARGETS; i++) {
enum pipe_format pformat = 0;
enum a3xx_color_fmt format = 0;
enum a3xx_color_swap swap = WZYX;

4
src/gallium/drivers/freedreno/a3xx/fd3_program.c
View file

@ -136,6 +136,8 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
int constmode;
int i, j, k;
debug_assert(nr <= ARRAY_SIZE(color_regid));
vp = fd3_emit_get_vp(emit);
if (emit->key.binning_pass) {
@ -207,7 +209,7 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
unsigned idx = sem2idx(sem);
if (sem2name(sem) != TGSI_SEMANTIC_COLOR)
continue;
assert(idx < 4);
debug_assert(idx < ARRAY_SIZE(color_regid));
color_regid[idx] = fp->outputs[i].regid;
}
}

4
src/gallium/drivers/freedreno/a4xx/fd4_blend.h
View file

@ -32,13 +32,15 @@
#include "pipe/p_state.h"
#include "pipe/p_context.h"
#include "freedreno_util.h"
struct fd4_blend_stateobj {
struct pipe_blend_state base;
struct {
uint32_t control;
uint32_t buf_info;
uint32_t blend_control;
} rb_mrt[8];
} rb_mrt[A4XX_MAX_RENDER_TARGETS];
uint32_t rb_fs_output;
};

2
src/gallium/drivers/freedreno/a4xx/fd4_draw.c
View file

@ -265,7 +265,7 @@ fd4_clear(struct fd_context *ctx, unsigned buffers,
ce = 0x0;
}
for (i = 0; i < 8; i++) {
for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
OUT_RING(ring, A4XX_RB_MRT_CONTROL_FASTCLEAR |
A4XX_RB_MRT_CONTROL_B11 |

2
src/gallium/drivers/freedreno/a4xx/fd4_emit.c
View file

@ -487,7 +487,7 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
struct fd4_blend_stateobj *blend = fd4_blend_stateobj(ctx->blend);
uint32_t i;
for (i = 0; i < 8; i++) {
for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
OUT_RING(ring, blend->rb_mrt[i].control);

2
src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
View file

@ -63,7 +63,7 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
tile_mode = TILE4_LINEAR;
}
for (i = 0; i < 8; i++) {
for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
enum a4xx_color_fmt format = 0;
enum a3xx_color_swap swap = WZYX;
struct fd_resource *rsc = NULL;

2
src/gallium/drivers/freedreno/freedreno_context.h
View file

@ -193,7 +193,7 @@ struct fd_context {
struct fd_program_stateobj solid_prog; // TODO move to screen?
/* shaders used by mem->gmem blits: */
struct fd_program_stateobj blit_prog[8]; // TODO move to screen?
struct fd_program_stateobj blit_prog[MAX_RENDER_TARGETS]; // TODO move to screen?
struct fd_program_stateobj blit_z, blit_zs;
/* do we need to mem2gmem before rendering. We don't, if for example,

15
src/gallium/drivers/freedreno/freedreno_gmem.c
View file

@ -82,7 +82,7 @@ total_size(uint8_t cbuf_cpp[], uint8_t zsbuf_cpp[2],
{
uint32_t total = 0, i;
for (i = 0; i < 4; i++) {
for (i = 0; i < MAX_RENDER_TARGETS; i++) {
if (cbuf_cpp[i]) {
gmem->cbuf_base[i] = align(total, 0x4000);
total = gmem->cbuf_base[i] + cbuf_cpp[i] * bin_w * bin_h;
@ -113,7 +113,7 @@ calculate_tiles(struct fd_context *ctx)
uint32_t nbins_x = 1, nbins_y = 1;
uint32_t bin_w, bin_h;
uint32_t max_width = bin_width(ctx);
uint8_t cbuf_cpp[4] = {0}, zsbuf_cpp[2] = {0};
uint8_t cbuf_cpp[MAX_RENDER_TARGETS] = {0}, zsbuf_cpp[2] = {0};
uint32_t i, j, t, xoff, yoff;
uint32_t tpp_x, tpp_y;
bool has_zs = !!(ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL));
@ -162,12 +162,17 @@ calculate_tiles(struct fd_context *ctx)
bin_w = align(width / nbins_x, 32);
}
if (fd_mesa_debug & FD_DBG_MSGS) {
debug_printf("binning input: cbuf cpp:");
for (i = 0; i < pfb->nr_cbufs; i++)
debug_printf(" %d", cbuf_cpp[i]);
debug_printf(", zsbuf cpp: %d; %dx%d\n",
zsbuf_cpp[0], width, height);
}
/* then find a bin width/height that satisfies the memory
* constraints:
*/
DBG("binning input: cbuf cpp: %d %d %d %d, zsbuf cpp: %d; %dx%d",
cbuf_cpp[0], cbuf_cpp[1], cbuf_cpp[2], cbuf_cpp[3], zsbuf_cpp[0],
width, height);
while (total_size(cbuf_cpp, zsbuf_cpp, bin_w, bin_h, gmem) > gmem_size) {
if (bin_w > bin_h) {
nbins_x++;

6
src/gallium/drivers/freedreno/freedreno_gmem.h
View file

@ -31,6 +31,8 @@
#include "pipe/p_context.h"
#include "freedreno_util.h"
/* per-pipe configuration for hw binning: */
struct fd_vsc_pipe {
struct fd_bo *bo;
@ -47,9 +49,9 @@ struct fd_tile {
struct fd_gmem_stateobj {
struct pipe_scissor_state scissor;
uint32_t cbuf_base[4];
uint32_t cbuf_base[MAX_RENDER_TARGETS];
uint32_t zsbuf_base[2];
uint8_t cbuf_cpp[4];
uint8_t cbuf_cpp[MAX_RENDER_TARGETS];
uint8_t zsbuf_cpp[2];
uint16_t bin_h, nbins_y;
uint16_t bin_w, nbins_x;

6
src/gallium/drivers/freedreno/freedreno_program.c
View file

@ -96,7 +96,11 @@ fd_prog_blit(struct pipe_context *pctx, int rts, bool depth)
{
int i;
struct ureg_src tc;
struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT);
struct ureg_program *ureg;
debug_assert(rts <= MAX_RENDER_TARGETS);
ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT);
if (!ureg)
return NULL;

6
src/gallium/drivers/freedreno/freedreno_util.h
View file

@ -54,6 +54,12 @@ enum adreno_stencil_op fd_stencil_op(unsigned op);
/* TBD if it is same on a2xx, but for now: */
#define MAX_MIP_LEVELS A3XX_MAX_MIP_LEVELS
#define A2XX_MAX_RENDER_TARGETS 1
#define A3XX_MAX_RENDER_TARGETS 4
#define A4XX_MAX_RENDER_TARGETS 8
/* for now until a4xx MRT support: */
#define MAX_RENDER_TARGETS A3XX_MAX_RENDER_TARGETS
#define FD_DBG_MSGS 0x0001
#define FD_DBG_DISASM 0x0002
#define FD_DBG_DCLEAR 0x0004