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intel/compiler: adjust task payload offsets as late as possible

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Otherwise passes which expect offsets to be in bytes (like
brw_nir_lower_mem_access_bit_sizes, called from brw_postprocess_nir)
may produce incorrect results.

Fixes 64-bit load/stores in task/mesh shaders.

Fixes: c36ae42e4c ("intel/compiler: Use nir_var_mem_task_payload")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16196>
(cherry picked from commit 42b551fe7f)
This commit is contained in:
Marcin Ślusarz 2022-05-23 17:09:33 +02:00 • committed by Dylan Baker
parent 02923d7685
commit a21cba54ca
2 changed files with 23 additions and 8 deletions
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2
.pick_status.json
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@ -76,7 +76,7 @@
"description": "intel/compiler: adjust task payload offsets as late as possible",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "c36ae42e4cccc925e5319afe41c4b8ba850730b4"
},

29
src/intel/compiler/brw_mesh.cpp
View file

@ -171,13 +171,26 @@ brw_nir_adjust_task_payload_offsets_instr(struct nir_builder *b,
}
}
static void
static bool
brw_nir_adjust_task_payload_offsets(nir_shader *nir)
{
nir_shader_instructions_pass(nir, brw_nir_adjust_task_payload_offsets_instr,
nir_metadata_block_index |
nir_metadata_dominance,
NULL);
return nir_shader_instructions_pass(nir,
brw_nir_adjust_task_payload_offsets_instr,
nir_metadata_block_index |
nir_metadata_dominance,
NULL);
}
static void
brw_nir_adjust_payload(nir_shader *shader, const struct brw_compiler *compiler)
{
/* Adjustment of task payload offsets must be performed *after* last pass
* which interprets them as bytes, because it changes their unit.
*/
bool adjusted = false;
NIR_PASS(adjusted, shader, brw_nir_adjust_task_payload_offsets);
if (adjusted) /* clean up the mess created by offset adjustments */
NIR_PASS_V(shader, nir_opt_constant_folding);
}
const unsigned *
@ -202,7 +215,6 @@ brw_compile_task(const struct brw_compiler *compiler,
BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID);
NIR_PASS_V(nir, brw_nir_lower_tue_outputs, &prog_data->map);
NIR_PASS_V(nir, brw_nir_adjust_task_payload_offsets);
const unsigned required_dispatch_width =
brw_required_dispatch_width(&nir->info, key->base.subgroup_size_type);
@ -226,6 +238,8 @@ brw_compile_task(const struct brw_compiler *compiler,
brw_postprocess_nir(shader, compiler, true /* is_scalar */, debug_enabled,
key->base.robust_buffer_access);
brw_nir_adjust_payload(shader, compiler);
v[simd] = new fs_visitor(compiler, params->log_data, mem_ctx, &key->base,
&prog_data->base.base, shader, dispatch_width,
debug_enabled);
@ -686,7 +700,6 @@ brw_compile_mesh(const struct brw_compiler *compiler,
BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID);
NIR_PASS_V(nir, brw_nir_lower_tue_inputs, params->tue_map);
NIR_PASS_V(nir, brw_nir_adjust_task_payload_offsets);
brw_compute_mue_map(nir, &prog_data->map);
NIR_PASS_V(nir, brw_nir_lower_mue_outputs, &prog_data->map);
@ -725,6 +738,8 @@ brw_compile_mesh(const struct brw_compiler *compiler,
brw_postprocess_nir(shader, compiler, true /* is_scalar */, debug_enabled,
key->base.robust_buffer_access);
brw_nir_adjust_payload(shader, compiler);
v[simd] = new fs_visitor(compiler, params->log_data, mem_ctx, &key->base,
&prog_data->base.base, shader, dispatch_width,
debug_enabled);