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i965: Move the post-HiZ-clear flush/stall to intel_hiz_exec

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This also changes it to be predicated so we only do the flush/stall on
clears and HiZ resolves.  The docs only say it's needed for clears but
empirical evidence says it's also needed for HiZ resolves.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Jason Ekstrand 2017-06-05 17:05:02 -07:00
parent 9cb6ac62fb
commit a2152775fd
2 changed files with 18 additions and 16 deletions
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18
src/mesa/drivers/dri/i965/brw_blorp.c
View file

@ -1098,6 +1098,24 @@ intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_CS_STALL);
} else if (brw->gen >= 8) {
/*
* From the Broadwell PRM, volume 7, "Depth Buffer Clear":
*
* "Depth buffer clear pass using any of the methods (WM_STATE,
* 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
* PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
* "set" before starting to render. DepthStall and DepthFlush are
* not needed between consecutive depth clear passes nor is it
* required if the depth clear pass was done with
* 'full_surf_clear' bit set in the 3DSTATE_WM_HZ_OP."
*
* TODO: Such as the spec says, this could be conditional.
*/
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_DEPTH_STALL);
}
}
}

16
src/mesa/drivers/dri/i965/gen8_depth_state.c
View file

@ -524,22 +524,6 @@ gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
OUT_BATCH(0);
ADVANCE_BATCH();
/*
* From the Broadwell PRM, volume 7, "Depth Buffer Clear":
*
* Depth buffer clear pass using any of the methods (WM_STATE, 3DSTATE_WM
* or 3DSTATE_WM_HZ_OP) must be followed by a PIPE_CONTROL command with
* DEPTH_STALL bit and Depth FLUSH bits "set" before starting to render.
* DepthStall and DepthFlush are not needed between consecutive depth
* clear passes nor is it required if th e depth clear pass was done with
* "full_surf_clear" bit set in the 3DSTATE_WM_HZ_OP.
*
* TODO: Such as the spec says, this could be conditional.
*/
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_DEPTH_STALL);
/* Mark this buffer as needing a TC flush, as we've rendered to it. */
brw_render_cache_set_add_bo(brw, mt->bo);