From a1d8837bade429cdabc5bdfd78e78b54b91afb70 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20=C5=9Alusarz?= Date: Fri, 3 Mar 2023 13:08:06 +0100 Subject: [PATCH] anv,intel/compiler/xe2: fill MESH_CONTROL.VPandRTAIndexAutostripEnable Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw_compiler.h | 1 + src/intel/compiler/brw_mesh.cpp | 72 +++++++++++++++++++++++++++++-- src/intel/vulkan/genX_pipeline.c | 5 ++- 3 files changed, 74 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index 8150fd6f2e1..854c75b7d2a 100644 --- a/src/intel/compiler/brw_compiler.h +++ b/src/intel/compiler/brw_compiler.h @@ -1253,6 +1253,7 @@ struct brw_mesh_prog_data { enum brw_mesh_index_format index_format; bool uses_drawid; + bool autostrip_enable; }; /* brw_any_prog_data is prog_data for any stage that maps to an API stage */ diff --git a/src/intel/compiler/brw_mesh.cpp b/src/intel/compiler/brw_mesh.cpp index ca8aa9a759c..f7ef0fb0ea7 100644 --- a/src/intel/compiler/brw_mesh.cpp +++ b/src/intel/compiler/brw_mesh.cpp @@ -848,9 +848,9 @@ brw_compute_mue_map(const struct brw_compiler *compiler, } if (outputs_written & BITFIELD64_BIT(VARYING_SLOT_VIEWPORT)) { - map->start_dw[VARYING_SLOT_VIEWPORT] = - map->per_primitive_start_dw + 2; - map->len_dw[VARYING_SLOT_VIEWPORT] = 1; + map->start_dw[VARYING_SLOT_VIEWPORT] = + map->per_primitive_start_dw + 2; + map->len_dw[VARYING_SLOT_VIEWPORT] = 1; } if (outputs_written & BITFIELD64_BIT(VARYING_SLOT_CULL_PRIMITIVE)) { @@ -1471,6 +1471,70 @@ brw_pack_primitive_indices(nir_shader *nir, void *data) data); } +static bool +brw_mesh_autostrip_enable(const struct brw_compiler *compiler, struct nir_shader *nir, + struct brw_mue_map *map) +{ + /* Auto-striping can be enabled when shader either doesn't write to + * RTA Index and VP Index or writes the same values for all primitives. + * Since determining whether shader writes the same value across the whole + * workgroup (not just subgroup!) is tricky, we do the simplest possible + * thing - say yes only when shader writes const values and they all match. + * + * TODO: improve this + */ + + if (compiler->devinfo->ver < 20) + return false; + + if (map->start_dw[VARYING_SLOT_VIEWPORT] < 0 && + map->start_dw[VARYING_SLOT_LAYER] < 0) + return true; + + nir_def *vp = NULL; + nir_def *layer = NULL; + + nir_foreach_function(function, nir) { + if (!function->impl) + continue; + + nir_foreach_block(block, function->impl) { + nir_foreach_instr(instr, block) { + if (instr->type != nir_instr_type_intrinsic) + continue; + + nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); + if (intrin->intrinsic != nir_intrinsic_store_per_primitive_output) + continue; + + struct nir_io_semantics io = nir_intrinsic_io_semantics(intrin); + bool is_vp = io.location == VARYING_SLOT_VIEWPORT; + bool is_layer = io.location == VARYING_SLOT_LAYER; + if (!is_vp && !is_layer) + continue; + + nir_src *src = &intrin->src[0]; + + if (!nir_src_is_const(*src)) + return false; + + nir_def **cmp; + if (is_vp) + cmp = &vp; + else + cmp = &layer; + + if (*cmp == NULL) + *cmp = src->ssa; + else if (*cmp != src->ssa) + return false; + } + } + } + + return true; +} + const unsigned * brw_compile_mesh(const struct brw_compiler *compiler, struct brw_compile_mesh_params *params) @@ -1512,6 +1576,8 @@ brw_compile_mesh(const struct brw_compiler *compiler, prog_data->index_format, key->compact_mue); brw_nir_lower_mue_outputs(nir, &prog_data->map); + prog_data->autostrip_enable = brw_mesh_autostrip_enable(compiler, nir, &prog_data->map); + brw_simd_selection_state simd_state{ .devinfo = compiler->devinfo, .prog_data = &prog_data->base, diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index 8b611eed734..4625ecd9541 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -1828,6 +1828,7 @@ emit_mesh_state(struct anv_graphics_pipeline *pipeline) assert(anv_pipeline_is_mesh(pipeline)); const struct anv_shader_bin *mesh_bin = pipeline->base.shaders[MESA_SHADER_MESH]; + const struct brw_mesh_prog_data *mesh_prog_data = get_mesh_prog_data(pipeline); anv_pipeline_emit(pipeline, final.mesh_control, GENX(3DSTATE_MESH_CONTROL), mc) { @@ -1836,10 +1837,12 @@ emit_mesh_state(struct anv_graphics_pipeline *pipeline) mc.ScratchSpaceBuffer = get_scratch_surf(&pipeline->base.base, MESA_SHADER_MESH, mesh_bin); mc.MaximumNumberofThreadGroups = 511; +#if GFX_VER >= 20 + mc.VPandRTAIndexAutostripEnable = mesh_prog_data->autostrip_enable; +#endif } const struct intel_device_info *devinfo = pipeline->base.base.device->info; - const struct brw_mesh_prog_data *mesh_prog_data = get_mesh_prog_data(pipeline); const struct intel_cs_dispatch_info mesh_dispatch = brw_cs_get_dispatch_info(devinfo, &mesh_prog_data->base, NULL);