fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-24 19:40:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

intel/fs: Assert that the gen4-6 plane restrictions are followed

Browse source 
The fall-back does not work correctly in SIMD16 mode and the register
allocator should ensure that we never hit this case anyway.

Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Jason Ekstrand 2018-05-16 17:30:04 -07:00
parent ed834aefa2
commit a1a850cd34
1 changed files with 8 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
src/intel/compiler/brw_fs_generator.cpp
View file

@ -817,8 +817,14 @@ fs_generator::generate_linterp(fs_inst *inst,
}
return true;
} else if (devinfo->has_pln &&
(devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
} else if (devinfo->has_pln) {
/* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
*
* "[DevSNB]:<src1> must be even register aligned.
*
* This restriction is lifted on Ivy Bridge.
*/
assert(devinfo->gen >= 7 || (delta_x.nr & 1) == 0);
brw_PLN(p, dst, interp, delta_x);
return false;