diff --git a/src/gallium/drivers/iris/iris_program.c b/src/gallium/drivers/iris/iris_program.c
index 5ba9bda6028..3822c56fd9f 100644
--- a/src/gallium/drivers/iris/iris_program.c
+++ b/src/gallium/drivers/iris/iris_program.c
@@ -1884,10 +1884,6 @@ iris_compile_vs(struct iris_screen *screen,
 
       brw_nir_analyze_ubo_ranges(screen->brw, nir, brw_prog_data->base.base.ubo_ranges);
 
-      brw_compute_vue_map(devinfo,
-                          &brw_prog_data->base.vue_map, nir->info.outputs_written,
-                          key->vue.layout, /* pos_slots */ 1);
-
       struct brw_vs_prog_key brw_key = iris_to_brw_vs_key(screen, key);
 
       struct brw_compile_vs_params params = {
diff --git a/src/intel/compiler/brw_compile_gs.cpp b/src/intel/compiler/brw_compile_gs.cpp
index 111ba9e48e1..9e24fabb900 100644
--- a/src/intel/compiler/brw_compile_gs.cpp
+++ b/src/intel/compiler/brw_compile_gs.cpp
@@ -163,6 +163,16 @@ brw_compile_gs(const struct brw_compiler *compiler,
                        &input_vue_map, inputs_read,
                        key->base.vue_layout, 1);
 
+   const uint32_t pos_slots =
+      (nir->info.per_view_outputs & VARYING_BIT_POS) ?
+      MAX2(1, util_bitcount(key->base.view_mask)) : 1;
+
+   brw_compute_vue_map(compiler->devinfo,
+                       &prog_data->base.vue_map,
+                       nir->info.outputs_written,
+                       key->base.vue_layout,
+                       pos_slots);
+
    brw_nir_apply_key(nir, compiler, &key->base, dispatch_width);
    brw_nir_lower_vue_inputs(nir, &input_vue_map);
    brw_nir_lower_vue_outputs(nir);
diff --git a/src/intel/compiler/brw_compile_tes.cpp b/src/intel/compiler/brw_compile_tes.cpp
index 642159f5fca..9166cb91e93 100644
--- a/src/intel/compiler/brw_compile_tes.cpp
+++ b/src/intel/compiler/brw_compile_tes.cpp
@@ -82,9 +82,13 @@ brw_compile_tes(const struct brw_compiler *compiler,
    brw_postprocess_nir(nir, compiler, debug_enabled,
                        key->base.robust_flags);
 
+   const uint32_t pos_slots =
+      (nir->info.per_view_outputs & VARYING_BIT_POS) ?
+      MAX2(1, util_bitcount(key->base.view_mask)) : 1;
+
    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
                        nir->info.outputs_written,
-                       key->base.vue_layout, 1);
+                       key->base.vue_layout, pos_slots);
 
    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
 
diff --git a/src/intel/compiler/brw_compile_vs.cpp b/src/intel/compiler/brw_compile_vs.cpp
index 2c9514bcf1d..a5ef4258097 100644
--- a/src/intel/compiler/brw_compile_vs.cpp
+++ b/src/intel/compiler/brw_compile_vs.cpp
@@ -248,6 +248,20 @@ brw_compile_vs(const struct brw_compiler *compiler,
 
    brw_prog_data_init(&prog_data->base.base, &params->base);
 
+   /* When using Primitive Replication for multiview, each view gets its own
+    * position slot.
+    */
+   const uint32_t pos_slots =
+      (nir->info.per_view_outputs & VARYING_BIT_POS) ?
+      MAX2(1, util_bitcount(key->base.view_mask)) : 1;
+
+   /* Only position is allowed to be per-view */
+   assert(!(nir->info.per_view_outputs & ~VARYING_BIT_POS));
+
+   brw_compute_vue_map(compiler->devinfo,
+                       &prog_data->base.vue_map, nir->info.outputs_written,
+                       key->base.vue_layout, pos_slots);
+
    brw_nir_apply_key(nir, compiler, &key->base, dispatch_width);
 
    prog_data->inputs_read = nir->info.inputs_read;
diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h
index c994d88c015..c265a0838b6 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -219,6 +219,12 @@ enum brw_robustness_flags {
 struct brw_base_prog_key {
    unsigned program_string_id;
 
+   /** Multiview mask
+    *
+    * Used to compute the number of position slots in the VUE
+    */
+   uint32_t view_mask;
+
    enum brw_robustness_flags robust_flags:2;
 
    bool uses_inline_push_addr:1;
@@ -232,7 +238,7 @@ struct brw_base_prog_key {
     */
    bool limit_trig_input_range:1;
 
-   unsigned padding:26;
+   uint64_t padding:58;
 };
 
 /**
@@ -294,7 +300,7 @@ struct brw_vs_prog_key {
     */
    bool no_vf_slot_compaction : 1;
 
-   uint32_t padding : 30;
+   uint64_t padding : 62;
 };
 
 /** The program key for Tessellation Control Shaders. */
@@ -421,7 +427,7 @@ struct brw_cs_prog_key {
     */
    bool lower_unaligned_dispatch:1;
 
-   uint32_t padding:31;
+   uint64_t padding:63;
 };
 
 struct brw_bs_prog_key {
@@ -432,6 +438,8 @@ struct brw_bs_prog_key {
     * shader.
     */
    uint32_t pipeline_ray_flags;
+
+   uint32_t padding;
 };
 
 /* brw_any_prog_key is any of the keys that map to an API stage */
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 325ff39e089..382aef52d80 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -1244,21 +1244,10 @@ anv_pipeline_compile_vs(const struct brw_compiler *compiler,
                         uint32_t view_mask,
                         char **error_str)
 {
-   /* When using Primitive Replication for multiview, each view gets its own
-    * position slot.
-    */
-   uint32_t pos_slots =
-      (vs_stage->nir->info.per_view_outputs & VARYING_BIT_POS) ?
-      MAX2(1, util_bitcount(view_mask)) : 1;
-
    /* Only position is allowed to be per-view */
    assert(!(vs_stage->nir->info.per_view_outputs & ~VARYING_BIT_POS));
 
-   brw_compute_vue_map(compiler->devinfo,
-                       &vs_stage->prog_data.vs.base.vue_map,
-                       vs_stage->nir->info.outputs_written,
-                       vs_stage->key.base.vue_layout,
-                       pos_slots);
+   vs_stage->key.vs.base.view_mask = view_mask;
 
    vs_stage->num_stats = 1;