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brw/nir: Treat some resource_intel as convergent
No shader-db changes on any Intel platform. No fossil-db changes on Ice Lake or Skylake. fossil-db: Lunar Lake Totals: Cycle count: 21653232202 -> 21653230858 (-0.00%); split: -0.00%, +0.00% Totals from 4 (0.00% of 553202) affected shaders: Cycle count: 14276568 -> 14275224 (-0.01%); split: -0.01%, +0.00% Meteor Lake, DG2, and Tiger Lake had similar results. (Meteor Lake shown) Totals: Instrs: 156453398 -> 156455123 (+0.00%); split: -0.00%, +0.00% Cycle count: 16904394153 -> 16904545026 (+0.00%); split: -0.00%, +0.00% Totals from 1189 (0.18% of 643905) affected shaders: Instrs: 502891 -> 504616 (+0.34%); split: -0.00%, +0.34% Cycle count: 1579688485 -> 1579839358 (+0.01%); split: -0.00%, +0.01% Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29884>
This commit is contained in:
Ian Romanick
parent
1b24612c57
commit
a13244e57b
1 changed files with 11 additions and 274 deletions
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@ -56,7 +56,6 @@ struct nir_to_brw_state {
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fs_builder bld;
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brw_reg *ssa_values;
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fs_inst **resource_insts;
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struct brw_fs_bind_info *ssa_bind_infos;
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brw_reg *uniform_values;
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brw_reg *system_values;
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@ -387,7 +386,6 @@ static void
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fs_nir_emit_impl(nir_to_brw_state &ntb, nir_function_impl *impl)
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{
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ntb.ssa_values = rzalloc_array(ntb.mem_ctx, brw_reg, impl->ssa_alloc);
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ntb.resource_insts = rzalloc_array(ntb.mem_ctx, fs_inst *, impl->ssa_alloc);
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ntb.ssa_bind_infos = rzalloc_array(ntb.mem_ctx, struct brw_fs_bind_info, impl->ssa_alloc);
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ntb.uniform_values = rzalloc_array(ntb.mem_ctx, brw_reg, impl->ssa_alloc);
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@ -1998,6 +1996,10 @@ get_nir_def(nir_to_brw_state &ntb, const nir_def &def, bool all_sources_uniform)
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is_scalar = get_nir_src(ntb, instr->src[0]).is_scalar;
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break;
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case nir_intrinsic_resource_intel:
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is_scalar = !def.divergent;
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break;
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default:
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break;
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}
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@ -4808,270 +4810,6 @@ brw_reduce_op_for_nir_reduction_op(nir_op op)
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}
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}
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struct rebuild_resource {
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unsigned idx;
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std::vector<nir_def *> array;
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const brw_reg *ssa_values;
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};
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static bool
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skip_rebuild_instr(nir_instr *instr)
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{
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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switch (intrin->intrinsic) {
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case nir_intrinsic_load_ubo_uniform_block_intel:
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case nir_intrinsic_load_ssbo_uniform_block_intel:
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case nir_intrinsic_load_global_constant_uniform_block_intel:
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/* Those intrinsic are generated using NoMask so we can trust their
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* destination registers are fully populated. No need to rematerialize
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* further.
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*/
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return true;
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default:
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return false;
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}
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}
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static bool
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add_rebuild_src(nir_src *src, void *state)
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{
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struct rebuild_resource *res = (struct rebuild_resource *) state;
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if (res->ssa_values[src->ssa->index].is_scalar)
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return true;
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for (nir_def *def : res->array) {
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if (def == src->ssa)
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return true;
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}
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if (!skip_rebuild_instr(src->ssa->parent_instr))
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nir_foreach_src(src->ssa->parent_instr, add_rebuild_src, state);
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res->array.push_back(src->ssa);
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return true;
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}
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static brw_reg
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try_rebuild_source(nir_to_brw_state &ntb, const brw::fs_builder &bld,
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nir_def *resource_def, bool a64 = false)
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{
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if (ntb.ssa_values[resource_def->index].is_scalar) {
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brw_reg r = ntb.ssa_values[resource_def->index];
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/* All users of try_rebuild_source expect an integer type. Smash the
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* type to an integer type with the same size.
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*/
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r.type = brw_type_with_size(BRW_TYPE_D, resource_def->bit_size);
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return component(r, 0);
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}
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/* Create a build at the location of the resource_intel intrinsic */
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fs_builder ubld = bld.exec_all().group(8 * reg_unit(ntb.devinfo), 0);
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struct rebuild_resource resources = {};
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resources.ssa_values = ntb.ssa_values;
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resources.idx = 0;
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if (!nir_foreach_src(resource_def->parent_instr,
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add_rebuild_src, &resources))
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return brw_reg();
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resources.array.push_back(resource_def);
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#if 0
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fprintf(stderr, "Trying remat :\n");
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for (unsigned i = 0; i < resources.array.size(); i++) {
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fprintf(stderr, " ");
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nir_print_instr(resources.array[i]->parent_instr, stderr);
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fprintf(stderr, "\n");
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}
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#endif
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for (unsigned i = 0; i < resources.array.size(); i++) {
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nir_def *def = resources.array[i];
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nir_instr *instr = def->parent_instr;
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switch (instr->type) {
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case nir_instr_type_load_const: {
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unreachable("load_const should already be is_scalar");
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}
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case nir_instr_type_alu: {
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nir_alu_instr *alu = nir_instr_as_alu(instr);
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/* Not supported ALU source count */
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if (nir_op_infos[alu->op].num_inputs > 3)
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break;
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brw_reg srcs[3];
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for (unsigned s = 0; s < nir_op_infos[alu->op].num_inputs; s++) {
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brw_reg reg;
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if (ntb.resource_insts[alu->src[s].src.ssa->index] == NULL) {
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reg = ntb.ssa_values[alu->src[s].src.ssa->index];
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assert(reg.is_scalar);
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srcs[s] = retype(offset(reg, ubld, alu->src[s].swizzle[0]),
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brw_int_type(brw_type_size_bytes(reg.type), false));
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} else {
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reg = ntb.resource_insts[alu->src[s].src.ssa->index]->dst;
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srcs[s] = offset(reg, ubld, alu->src[s].swizzle[0]);
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}
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assert(srcs[s].file != BAD_FILE);
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}
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const enum brw_reg_type utype0 =
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brw_type_with_size(BRW_TYPE_UD,
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brw_type_size_bits(srcs[0].type));
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const enum brw_reg_type utype1 =
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nir_op_infos[alu->op].num_inputs > 1 ?
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brw_type_with_size(BRW_TYPE_UD,
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brw_type_size_bits(srcs[1].type)) :
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BRW_TYPE_UD;
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switch (alu->op) {
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case nir_op_iadd:
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if (srcs[0].file != IMM) {
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ubld.ADD(retype(srcs[0], utype0),
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retype(srcs[1], utype1),
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&ntb.resource_insts[def->index]);
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} else {
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ubld.ADD(retype(srcs[1], utype1),
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retype(srcs[0], utype0),
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&ntb.resource_insts[def->index]);
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}
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break;
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case nir_op_iadd3: {
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brw_reg dst = ubld.vgrf(srcs[0].type);
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ntb.resource_insts[def->index] =
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ubld.ADD3(dst,
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srcs[1].file == IMM ? srcs[1] : srcs[0],
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srcs[1].file == IMM ? srcs[0] : srcs[1],
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srcs[2]);
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break;
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}
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case nir_op_ushr:
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ubld.SHR(retype(srcs[0], utype0),
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retype(srcs[1], utype1),
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&ntb.resource_insts[def->index]);
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break;
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case nir_op_iand:
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ubld.AND(retype(srcs[0], utype0),
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retype(srcs[1], utype1),
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&ntb.resource_insts[def->index]);
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break;
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case nir_op_ishl:
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ubld.SHL(retype(srcs[0], utype0),
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retype(srcs[1], utype1),
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&ntb.resource_insts[def->index]);
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break;
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case nir_op_mov:
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break;
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case nir_op_ult32: {
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if (brw_type_size_bits(srcs[0].type) != 32)
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break;
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brw_reg dst = ubld.vgrf(utype0);
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ntb.resource_insts[def->index] =
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ubld.CMP(dst,
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retype(srcs[0], utype0),
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retype(srcs[1], utype1),
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brw_cmod_for_nir_comparison(alu->op));
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break;
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}
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case nir_op_b2i32:
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ubld.MOV(negate(retype(srcs[0], BRW_TYPE_D)),
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&ntb.resource_insts[def->index]);
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break;
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case nir_op_unpack_64_2x32_split_x:
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ubld.MOV(subscript(srcs[0], BRW_TYPE_D, 0),
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&ntb.resource_insts[def->index]);
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break;
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case nir_op_unpack_64_2x32_split_y:
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ubld.MOV(subscript(srcs[0], BRW_TYPE_D, 1),
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&ntb.resource_insts[def->index]);
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break;
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case nir_op_pack_64_2x32_split: {
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brw_reg dst = ubld.vgrf(BRW_TYPE_Q);
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ntb.resource_insts[def->index] =
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ubld.emit(FS_OPCODE_PACK, dst, srcs[0], srcs[1]);
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}
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default:
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break;
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}
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break;
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}
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case nir_instr_type_intrinsic: {
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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switch (intrin->intrinsic) {
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case nir_intrinsic_resource_intel:
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ntb.resource_insts[def->index] =
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ntb.resource_insts[intrin->src[1].ssa->index];
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break;
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case nir_intrinsic_load_uniform: {
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if (!nir_src_is_const(intrin->src[0]))
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break;
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unreachable("load_uniform should already be is_scalar");
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}
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case nir_intrinsic_load_inline_data_intel: {
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unreachable("load_mesh_inline_data_intel should already be is_scalar");
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}
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case nir_intrinsic_load_btd_local_arg_addr_intel: {
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unreachable("load_btd_local_arg_addr_intel should already be is_scalar");
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}
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case nir_intrinsic_load_btd_global_arg_addr_intel: {
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unreachable("load_btd_global_arg_addr_intel should already be is_scalar");
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}
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case nir_intrinsic_load_reloc_const_intel: {
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unreachable("load_reloc_const_intel should already be is_scalar");
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}
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case nir_intrinsic_load_ubo_uniform_block_intel:
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case nir_intrinsic_load_ssbo_uniform_block_intel: {
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unreachable("load_{ubo,ssbo}_uniform_block_intel should already be is_scalar");
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}
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default:
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break;
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}
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break;
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}
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default:
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break;
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}
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if (ntb.resource_insts[def->index] == NULL) {
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#if 0
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if (a64) {
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fprintf(stderr, "Tried remat :\n");
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for (unsigned i = 0; i < resources.array.size(); i++) {
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fprintf(stderr, " ");
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nir_print_instr(resources.array[i]->parent_instr, stderr);
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fprintf(stderr, "\n");
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}
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fprintf(stderr, "failed at! : ");
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nir_print_instr(instr, stderr);
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fprintf(stderr, "\n");
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}
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#endif
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return brw_reg();
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}
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}
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assert(ntb.resource_insts[resource_def->index] != NULL);
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return component(ntb.resource_insts[resource_def->index]->dst, 0);
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}
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static brw_reg
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get_nir_image_intrinsic_image(nir_to_brw_state &ntb, const brw::fs_builder &bld,
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nir_intrinsic_instr *instr)
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@ -6009,7 +5747,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb,
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const fs_builder xbld = dest.is_scalar ? bld.scalar_group() : bld;
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switch (instr->intrinsic) {
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case nir_intrinsic_resource_intel:
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case nir_intrinsic_resource_intel: {
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ntb.ssa_bind_infos[instr->def.index].valid = true;
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ntb.ssa_bind_infos[instr->def.index].bindless =
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(nir_intrinsic_resource_access_intel(instr) &
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@ -6021,16 +5759,18 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb,
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ntb.ssa_bind_infos[instr->def.index].binding =
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nir_intrinsic_binding(instr);
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brw_reg src = get_nir_src(ntb, instr->src[1]);
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if (nir_intrinsic_resource_access_intel(instr) &
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nir_resource_intel_non_uniform) {
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ntb.uniform_values[instr->def.index] = brw_reg();
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} else if (!src.is_scalar) {
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ntb.uniform_values[instr->def.index] = bld.emit_uniformize(src);
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} else {
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ntb.uniform_values[instr->def.index] =
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try_rebuild_source(ntb, bld, instr->src[1].ssa);
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ntb.uniform_values[instr->def.index] = src;
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}
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ntb.ssa_values[instr->def.index] =
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get_nir_src(ntb, instr->src[1]);
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ntb.ssa_values[instr->def.index] = src;
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break;
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}
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case nir_intrinsic_load_reg:
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case nir_intrinsic_store_reg:
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@ -6038,9 +5778,6 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb,
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break;
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case nir_intrinsic_load_global_constant_uniform_block_intel:
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ntb.uniform_values[instr->src[0].ssa->index] =
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try_rebuild_source(ntb, bld, instr->src[0].ssa, true);
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FALLTHROUGH;
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case nir_intrinsic_load_ssbo_uniform_block_intel:
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case nir_intrinsic_load_shared_uniform_block_intel:
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case nir_intrinsic_load_global_block_intel:
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