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intel/eu/gen12: Implement immediate 64 bit constant encoding.

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On Gen12, 64 bit immediate constants are loaded in reverse order. Lower
32 bit gets loaded from bit 96-127 and higher 32 bits from 64-95 in
instruction encoding.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Co-authored-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Sagar Ghuge 2018-11-15 16:19:39 -08:00 • committed by Francisco Jerez
parent 5291283af0
commit a12533f2ce
1 changed files with 13 additions and 2 deletions
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15
src/intel/compiler/brw_inst.h
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@ -1136,7 +1136,13 @@ brw_inst_set_imm_df(const struct gen_device_info *devinfo,
} dt;
(void) devinfo;
dt.d = value;
brw_inst_set_bits(insn, 127, 64, dt.u);
if (devinfo->gen >= 12) {
brw_inst_set_bits(insn, 95, 64, dt.u >> 32);
brw_inst_set_bits(insn, 127, 96, dt.u & 0xFFFFFFFF);
} else {
brw_inst_set_bits(insn, 127, 64, dt.u);
}
}
static inline void
@ -1144,7 +1150,12 @@ brw_inst_set_imm_uq(const struct gen_device_info *devinfo,
brw_inst *insn, uint64_t value)
{
(void) devinfo;
brw_inst_set_bits(insn, 127, 64, value);
if (devinfo->gen >= 12) {
brw_inst_set_bits(insn, 95, 64, value >> 32);
brw_inst_set_bits(insn, 127, 96, value & 0xFFFFFFFF);
} else {
brw_inst_set_bits(insn, 127, 64, value);
}
}
/** @} */