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etnaviv: linker: handle scenario where there are FS inputs without matching VS output

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If there is a FS input but no VS output the behavior is undefined
but okay. Use a register 0 (position) for such cases.

glsl-routing test triggers it with e.g. the following subtest.

Test: VS(C0 -- T0 -- T2 -- T4 T5)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)

This will now end with following linker debug output:

link result:
  vs  -> fs  comps use     pa_attr
  t1  -> t1  xyzw  0,0,0,0 0x000002f1
  t2  -> t2  xyzw  0,0,0,0 0x000002f1
  t0  -> t3  xyzw  0,0,0,0 0x000002f1
  t3  -> t4  xyzw  0,0,0,0 0x000002f1
  t0  -> t5  xyzw  0,0,0,0 0x000002f1
  t4  -> t6  xyzw  0,0,0,0 0x000002f1
  t5  -> t7  xyzw  0,0,0,0 0x000002f1

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24030>
This commit is contained in:
Christian Gmeiner 2023-07-06 08:08:16 +02:00 • committed by Marge Bot
parent ba0ceb3be3
commit a11501e014
2 changed files with 5 additions and 6 deletions
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1
src/etnaviv/ci/etnaviv-gc2000-fails.txt
View file

@ -167,7 +167,6 @@ shaders@glsl-kwin-blur-2,Crash
shaders@glsl-max-varyings,Crash
shaders@glsl-max-varyings >max_varying_components,Crash
shaders@glsl-novertexdata,Fail
shaders@glsl-routing,Crash
shaders@glsl-uniform-interstage-limits@subdivide 5- statechanges,Timeout
shaders@glsl-uniform-interstage-limits@subdivide 5,Timeout
shaders@glsl-vs-point-size,Fail

10
src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c
View file

@ -1322,11 +1322,11 @@ etna_link_shader(struct etna_shader_link_info *info,
* but that one removes all FS inputs ... why?
*/
} else {
if (vsio == NULL) { /* not found -- link error */
BUG("Semantic value not found in vertex shader outputs\n");
return true;
}
varying->reg = vsio->reg;
/* pick a random register to use if there is no VS output */
if (vsio == NULL)
varying->reg = 0;
else
varying->reg = vsio->reg;
}
comp_ofs += varying->num_components;