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radeonsi: implement EXPCLEAR optimization for depth
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
parent
f05fe294e7
commit
a10c8db715
5 changed files with 23 additions and 2 deletions
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@ -191,6 +191,7 @@ struct r600_texture {
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/* Depth buffer compression and fast clear. */
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struct r600_resource *htile_buffer;
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bool depth_cleared; /* if it was cleared at least once */
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float depth_clear_value;
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bool non_disp_tiling; /* R600-Cayman only */
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@ -362,6 +362,12 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
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zsbuf->u.tex.level == 0 &&
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zsbuf->u.tex.first_layer == 0 &&
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zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
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/* Need to disable EXPCLEAR temporarily if clearing
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* to a new value. */
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if (zstex->depth_cleared && zstex->depth_clear_value != depth) {
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sctx->db_depth_disable_expclear = true;
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}
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zstex->depth_clear_value = depth;
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sctx->framebuffer.atom.dirty = true; /* updates DB_DEPTH_CLEAR */
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sctx->db_depth_clear = true;
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@ -373,7 +379,11 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
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buffers, color, depth, stencil);
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si_blitter_end(ctx);
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sctx->db_depth_clear = false;
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if (sctx->db_depth_clear) {
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sctx->db_depth_clear = false;
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sctx->db_depth_disable_expclear = false;
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zstex->depth_cleared = true;
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}
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}
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static void si_clear_render_target(struct pipe_context *ctx,
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@ -165,6 +165,7 @@ struct si_context {
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unsigned dbcb_copy_sample;
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bool db_inplace_flush_enabled;
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bool db_depth_clear;
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bool db_depth_disable_expclear;
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};
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/* si_blit.c */
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@ -1823,7 +1823,8 @@ static void si_init_depth_surface(struct si_context *sctx,
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/* HiZ aka depth buffer htile */
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/* use htile only for first level */
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if (rtex->htile_buffer && !level) {
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z_info |= S_028040_TILE_SURFACE_ENABLE(1);
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z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
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S_028040_ALLOW_EXPCLEAR(1);
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/* This is optimal for the clear value of 1.0 and using
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* the LESS and LEQUAL test functions. Set this to 0
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@ -758,6 +758,14 @@ static void si_state_draw(struct si_context *sctx,
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si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, 0);
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}
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/* DB_RENDER_OVERRIDE2 */
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if (sctx->db_depth_disable_expclear) {
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si_pm4_set_reg(pm4, R_028010_DB_RENDER_OVERRIDE2,
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S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
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} else {
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si_pm4_set_reg(pm4, R_028010_DB_RENDER_OVERRIDE2, 0);
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}
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if (info->count_from_stream_output) {
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struct r600_so_target *t =
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(struct r600_so_target*)info->count_from_stream_output;
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