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i965/hsw: Initialize SLM index in state register
For Haswell, we need to initialize the SLM index in the state register. This can be copied out of the CS header dword 0. v2: * Use UW move to avoid changing upper 16-bits of sr0.1 (mattst88) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94081 Fixes: piglit arb_compute_shader/execution/shared-atomics.shader_test Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Cc: "11.2" <mesa-stable@lists.freedesktop.org> Tested-by: Ilia Mirkin <imirkin@alum.mit.edu> (v1) Reviewed-by: Matt Turner <mattst88@gmail.com>
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2 changed files with 23 additions and 0 deletions
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@ -5470,6 +5470,13 @@ fs_visitor::run_cs()
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if (shader_time_index >= 0)
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if (shader_time_index >= 0)
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emit_shader_time_begin();
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emit_shader_time_begin();
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if (devinfo->is_haswell && prog_data->total_shared > 0) {
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/* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
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const fs_builder abld = bld.exec_all().group(1, 0);
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abld.MOV(retype(suboffset(brw_sr0_reg(), 1), BRW_REGISTER_TYPE_UW),
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suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW), 1));
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}
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emit_nir_code();
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emit_nir_code();
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if (failed)
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if (failed)
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@ -739,6 +739,22 @@ brw_notification_reg(void)
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WRITEMASK_X);
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WRITEMASK_X);
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}
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}
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static inline struct brw_reg
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brw_sr0_reg(void)
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{
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return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
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BRW_ARF_STATE,
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0,
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0,
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0,
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BRW_REGISTER_TYPE_UD,
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BRW_VERTICAL_STRIDE_8,
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BRW_WIDTH_8,
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BRW_HORIZONTAL_STRIDE_1,
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BRW_SWIZZLE_XYZW,
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WRITEMASK_XYZW);
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}
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static inline struct brw_reg
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static inline struct brw_reg
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brw_acc_reg(unsigned width)
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brw_acc_reg(unsigned width)
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{
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{
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