From a0e857c7682e134034a7f416120c4deeed6754d7 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 29 Jan 2020 14:38:55 +0100 Subject: [PATCH] ac/nir: split 8-bit SSBO stores on GFX6 Due to possible alignment issues, make sure to split stores of 8-bit vectors. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: (cherry picked from commit c6bf1597d1e8abf122371118b04a85ee0aa6b3d5) --- .pick_status.json | 2 +- src/amd/llvm/ac_nir_to_llvm.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/.pick_status.json b/.pick_status.json index 1ec5a169f09..20502b40e08 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -2371,7 +2371,7 @@ "description": "ac/nir: split 8-bit SSBO stores on GFX6", "nominated": false, "nomination_type": null, - "resolution": 4, + "resolution": 1, "master_sha": null, "because_sha": null }, diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 577a1b6cd75..6acef5e7fb7 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -1734,6 +1734,15 @@ static void visit_store_ssbo(struct ac_nir_context *ctx, count = 1; num_bytes = 2; } + + /* Due to alignment issues, split stores of 8-bit vectors. */ + if (ctx->ac.chip_class == GFX6 && + elem_size_bytes == 1 && count > 1) { + writemask |= ((1u << (count - 1)) - 1u) << (start + 1); + count = 1; + num_bytes = 1; + } + data = extract_vector_range(&ctx->ac, base_data, start, count); offset = LLVMBuildAdd(ctx->ac.builder, base_offset,