fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-08 11:18:08 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

intel/fs/xe2+: Update uses of pixel/sample mask from PS thread payload.

Browse source 
Note from Caio: proper handling of brw_sample_mask_reg
will appear in later patches.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26606>
This commit is contained in:
Francisco Jerez 2022-06-11 17:36:09 -07:00 • committed by Caio Oliveira
parent 6dae56cc57
commit a0ae3c0dba
2 changed files with 16 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
src/intel/compiler/brw_fs.cpp
View file

@ -4462,6 +4462,7 @@ brw_sample_mask_reg(const fs_builder &bld)
return brw_flag_subreg(sample_mask_flag_subreg(s) + bld.group() / 16); return brw_flag_subreg(sample_mask_flag_subreg(s) + bld.group() / 16);
} else { } else {
assert(s.devinfo->ver >= 6 && bld.dispatch_width() <= 16); assert(s.devinfo->ver >= 6 && bld.dispatch_width() <= 16);
assert(s.devinfo->ver < 20);
return retype(brw_vec1_grf((bld.group() >= 16 ? 2 : 1), 7), return retype(brw_vec1_grf((bld.group() >= 16 ? 2 : 1), 7),
BRW_REGISTER_TYPE_UW); BRW_REGISTER_TYPE_UW);
} }
@ -7020,8 +7021,14 @@ fs_visitor::run_fs(bool allow_spilling, bool do_rep_send)
if (wm_prog_data->uses_kill) { if (wm_prog_data->uses_kill) {
const unsigned lower_width = MIN2(dispatch_width, 16); const unsigned lower_width = MIN2(dispatch_width, 16);
for (unsigned i = 0; i < dispatch_width / lower_width; i++) { for (unsigned i = 0; i < dispatch_width / lower_width; i++) {
/* According to the "PS Thread Payload for Normal
* Dispatch" pages on the BSpec, the dispatch mask is
* stored in R0.15/R1.15 on gfx20+ and in R1.7/R2.7 on
* gfx6+.
*/
const fs_reg dispatch_mask = const fs_reg dispatch_mask =
devinfo->ver >= 6 ? brw_vec1_grf((i ? 2 : 1), 7) : devinfo->ver >= 20 ? xe2_vec1_grf(i, 15) :
devinfo->ver >= 6 ? brw_vec1_grf(i + 1, 7) :
brw_vec1_grf(0, 0); brw_vec1_grf(0, 0);
bld.exec_all().group(1, 0) bld.exec_all().group(1, 0)
.MOV(brw_sample_mask_reg(bld.group(lower_width, i)), .MOV(brw_sample_mask_reg(bld.group(lower_width, i)),

11
src/intel/compiler/brw_fs_nir.cpp
View file

@ -283,10 +283,15 @@ emit_system_values_block(nir_to_brw_state &ntb, nir_block *block)
for (unsigned i = 0; i < DIV_ROUND_UP(s.dispatch_width, 16); i++) { for (unsigned i = 0; i < DIV_ROUND_UP(s.dispatch_width, 16); i++) {
const fs_builder hbld = abld.group(MIN2(16, s.dispatch_width), i); const fs_builder hbld = abld.group(MIN2(16, s.dispatch_width), i);
/* According to the "PS Thread Payload for Normal
* Dispatch" pages on the BSpec, the dispatch mask is
* stored in R0.15/R1.15 on gfx20+ and in R1.7/R2.7 on
* gfx6+.
*/
const struct brw_reg reg = s.devinfo->ver >= 20 ?
xe2_vec1_grf(i, 15) : brw_vec1_grf(i + 1, 7);
hbld.SHR(offset(shifted, hbld, i), hbld.SHR(offset(shifted, hbld, i),
stride(retype(brw_vec1_grf(1 + i, 7), stride(retype(reg, BRW_REGISTER_TYPE_UB), 1, 8, 0),
BRW_REGISTER_TYPE_UB),
1, 8, 0),
brw_imm_v(0x76543210)); brw_imm_v(0x76543210));
} }