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radeonsi: precompute GS_OUT_PRIM in advance

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We don't have to do it every draw now if the rasterized prim type
doesn't change.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18195>
This commit is contained in:
Marek Olšák 2022-08-14 06:55:19 -04:00 • committed by Marge Bot
parent 7144621e94
commit a070a09d00
2 changed files with 14 additions and 32 deletions
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15
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -48,6 +48,9 @@ extern "C" {
#define ATI_VENDOR_ID 0x1002 #define ATI_VENDOR_ID 0x1002
#define SI_NOT_QUERY 0xffffffff #define SI_NOT_QUERY 0xffffffff
/* special primitive types */
#define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
/* The base vertex and primitive restart can be any number, but we must pick /* The base vertex and primitive restart can be any number, but we must pick
* one which will mean "unknown" for the purpose of state tracking and * one which will mean "unknown" for the purpose of state tracking and
* the number shouldn't be a commonly-used one. */ * the number shouldn't be a commonly-used one. */
@ -1163,6 +1166,7 @@ struct si_context {
unsigned last_vs_state; unsigned last_vs_state;
unsigned last_gs_state; unsigned last_gs_state;
enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */ enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
unsigned gs_out_prim;
struct si_small_prim_cull_info last_small_prim_cull_info; struct si_small_prim_cull_info last_small_prim_cull_info;
struct si_resource *small_prim_cull_info_buf; struct si_resource *small_prim_cull_info_buf;
@ -2106,11 +2110,18 @@ static inline void
si_set_rasterized_prim(struct si_context *sctx, enum pipe_prim_type rast_prim) si_set_rasterized_prim(struct si_context *sctx, enum pipe_prim_type rast_prim)
{ {
if (rast_prim != sctx->current_rast_prim) { if (rast_prim != sctx->current_rast_prim) {
if (util_prim_is_points_or_lines(sctx->current_rast_prim) != bool is_rect = rast_prim == SI_PRIM_RECTANGLE_LIST;
util_prim_is_points_or_lines(rast_prim)) bool is_points = rast_prim == PIPE_PRIM_POINTS;
bool is_lines = util_prim_is_lines(rast_prim);
bool is_triangles = util_rast_prim_is_triangles(rast_prim);
if ((is_points || is_lines) != util_prim_is_points_or_lines(sctx->current_rast_prim))
si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband); si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
sctx->current_rast_prim = rast_prim; sctx->current_rast_prim = rast_prim;
sctx->gs_out_prim = is_triangles ? V_028A6C_TRISTRIP :
is_lines ? V_028A6C_LINESTRIP :
is_rect ? V_028A6C_RECTLIST : V_028A6C_POINTLIST;
sctx->do_update_shaders = true; sctx->do_update_shaders = true;
} }
} }

31
src/gallium/drivers/radeonsi/si_state_draw.cpp
View file

@ -48,9 +48,6 @@
#error "Unknown gfx level" #error "Unknown gfx level"
#endif #endif
/* special primitive types */
#define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
template<int NUM_INTERP> template<int NUM_INTERP>
static void si_emit_spi_map(struct si_context *sctx) static void si_emit_spi_map(struct si_context *sctx)
{ {
@ -1123,32 +1120,6 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
return ia_multi_vgt_param; return ia_multi_vgt_param;
} }
ALWAYS_INLINE
static unsigned si_conv_prim_to_gs_out(unsigned mode)
{
static const int prim_conv[] = {
[PIPE_PRIM_POINTS] = V_028A6C_POINTLIST,
[PIPE_PRIM_LINES] = V_028A6C_LINESTRIP,
[PIPE_PRIM_LINE_LOOP] = V_028A6C_LINESTRIP,
[PIPE_PRIM_LINE_STRIP] = V_028A6C_LINESTRIP,
[PIPE_PRIM_TRIANGLES] = V_028A6C_TRISTRIP,
[PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_TRISTRIP,
[PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_TRISTRIP,
[PIPE_PRIM_QUADS] = V_028A6C_TRISTRIP,
[PIPE_PRIM_QUAD_STRIP] = V_028A6C_TRISTRIP,
[PIPE_PRIM_POLYGON] = V_028A6C_TRISTRIP,
[PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_LINESTRIP,
[PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_LINESTRIP,
[PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_TRISTRIP,
[PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_TRISTRIP,
[PIPE_PRIM_PATCHES] = V_028A6C_POINTLIST,
[SI_PRIM_RECTANGLE_LIST] = V_028A6C_RECTLIST,
};
assert(mode < ARRAY_SIZE(prim_conv));
return prim_conv[mode];
}
/* rast_prim is the primitive type after GS. */ /* rast_prim is the primitive type after GS. */
template<amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG> ALWAYS_INLINE template<amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG> ALWAYS_INLINE
static void si_emit_rasterizer_prim_state(struct si_context *sctx) static void si_emit_rasterizer_prim_state(struct si_context *sctx)
@ -1173,7 +1144,7 @@ static void si_emit_rasterizer_prim_state(struct si_context *sctx)
value); value);
} }
unsigned gs_out_prim = si_conv_prim_to_gs_out(rast_prim); unsigned gs_out_prim = sctx->gs_out_prim;
if (unlikely(gs_out_prim != sctx->last_gs_out_prim && (NGG || HAS_GS))) { if (unlikely(gs_out_prim != sctx->last_gs_out_prim && (NGG || HAS_GS))) {
if (GFX_VERSION >= GFX11) if (GFX_VERSION >= GFX11)
radeon_set_uconfig_reg(R_030998_VGT_GS_OUT_PRIM_TYPE, gs_out_prim); radeon_set_uconfig_reg(R_030998_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);