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radv: update color/ds clear metadata in ME

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It's probably sligthly better because loading the clear registers
is likely more frequent than updating them.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40341>
This commit is contained in:
Samuel Pitoiset 2026-03-20 10:54:05 +01:00 • committed by Marge Bot
parent fd019c24e9
commit a0471ddad8
1 changed files with 15 additions and 3 deletions
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18
src/amd/vulkan/radv_cmd_buffer.c
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@ -5038,6 +5038,7 @@ radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image
VkImageAspectFlags aspects)
{
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
struct radv_cmd_stream *cs = cmd_buffer->cs;
uint32_t level_count = vk_image_subresource_level_count(&image->vk, range);
@ -5046,7 +5047,7 @@ radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image
/* Use the fastest way when both aspects are used. */
ASSERTED unsigned cdw_end =
radv_cs_write_data_head(device, cs, V_370_PFP, va, 2 * level_count, cmd_buffer->state.predicating);
radv_cs_write_data_head(device, cs, V_370_ME, va, 2 * level_count, cmd_buffer->state.predicating);
radeon_begin(cs);
@ -5071,9 +5072,14 @@ radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image
value = ds_clear_value.stencil;
}
radv_write_data(cmd_buffer, V_370_PFP, va, 1, &value, cmd_buffer->state.predicating);
radv_write_data(cmd_buffer, V_370_ME, va, 1, &value, cmd_buffer->state.predicating);
}
}
if (cmd_buffer->qf == RADV_QUEUE_GENERAL && pdev->info.has_load_ctx_reg_pkt) {
radeon_check_space(device->ws, cs->b, 2);
ac_emit_cp_pfp_sync_me(cs->b, cmd_buffer->state.predicating);
}
}
void
@ -5298,6 +5304,7 @@ radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_im
const VkImageSubresourceRange *range, uint32_t color_values[2])
{
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
struct radv_cmd_stream *cs = cmd_buffer->cs;
uint32_t level_count = vk_image_subresource_level_count(&image->vk, range);
@ -5307,7 +5314,7 @@ radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_im
uint64_t va = radv_image_get_fast_clear_va(image, range->baseMipLevel);
ASSERTED unsigned cdw_end =
radv_cs_write_data_head(device, cs, V_370_PFP, va, 2 * level_count, cmd_buffer->state.predicating);
radv_cs_write_data_head(device, cs, V_370_ME, va, 2 * level_count, cmd_buffer->state.predicating);
radeon_begin(cs);
@ -5318,6 +5325,11 @@ radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_im
radeon_end();
assert(cs->b->cdw == cdw_end);
if (cmd_buffer->qf == RADV_QUEUE_GENERAL && pdev->info.has_load_ctx_reg_pkt) {
radeon_check_space(device->ws, cs->b, 2);
ac_emit_cp_pfp_sync_me(cs->b, cmd_buffer->state.predicating);
}
} else {
/* Some default value we can set in the update. */
assert(color_values[0] == 0 && color_values[1] == 0);