fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-24 21:50:12 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

aco: Set +wavefrontsize64 for LLVM disassembler in GFX10 wave64 mode.

Browse source 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
This commit is contained in:
Timur Kristóf 2019-09-21 17:58:08 +02:00
parent fa41a51891
commit a01d796de4
4 changed files with 15 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/amd/compiler/aco_instruction_selection_setup.cpp
View file

@ -1241,6 +1241,7 @@ setup_isel_context(Program* program,
program->info = info;
program->chip_class = options->chip_class;
program->family = options->family;
program->wave_size = options->wave_size;
program->sgpr_limit = options->chip_class >= GFX8 ? 102 : 104;
if (options->family == CHIP_TONGA || options->family == CHIP_ICELAND)
program->sgpr_limit = 94; /* workaround hardware bug */

2
src/amd/compiler/aco_interface.cpp
View file

@ -147,7 +147,7 @@ void aco_compile_shader(unsigned shader_count,
std::string disasm;
if (get_disasm) {
std::ostringstream stream;
aco::print_asm(program.get(), code, exec_size / 4u, options->family, stream);
aco::print_asm(program.get(), code, exec_size / 4u, stream);
stream << '\0';
disasm = stream.str();
size += disasm.size();

5
src/amd/compiler/aco_ir.h
View file

@ -1069,6 +1069,7 @@ public:
struct radv_shader_info *info;
enum chip_class chip_class;
enum radeon_family family;
unsigned wave_size;
Stage stage; /* Stage */
bool needs_exact = false; /* there exists an instruction with disable_wqm = true */
bool needs_wqm = false; /* there exists a p_wqm instruction */
@ -1141,8 +1142,8 @@ void spill(Program* program, live& live_vars, const struct radv_nir_compiler_opt
void insert_wait_states(Program* program);
void insert_NOPs(Program* program);
unsigned emit_program(Program* program, std::vector<uint32_t>& code);
void print_asm(Program *program, std::vector<uint32_t>& binary, unsigned exec_size,
enum radeon_family family, std::ostream& out);
void print_asm(Program *program, std::vector<uint32_t>& binary,
unsigned exec_size, std::ostream& out);
void validate(Program* program, FILE *output);
bool validate_ra(Program* program, const struct radv_nir_compiler_options *options, FILE *output);
#ifndef NDEBUG

14
src/amd/compiler/aco_print_asm.cpp
View file

@ -9,7 +9,7 @@
namespace aco {
void print_asm(Program *program, std::vector<uint32_t>& binary,
unsigned exec_size, enum radeon_family family, std::ostream& out)
unsigned exec_size, std::ostream& out)
{
std::vector<bool> referenced_blocks(program->blocks.size());
referenced_blocks[0] = true;
@ -30,9 +30,15 @@ void print_asm(Program *program, std::vector<uint32_t>& binary,
symbols.emplace_back(block.offset * 4, llvm::StringRef(block_names[block_names.size() - 1].data()), 0);
}
LLVMDisasmContextRef disasm = LLVMCreateDisasmCPU("amdgcn-mesa-mesa3d",
ac_get_llvm_processor_name(family),
&symbols, 0, NULL, NULL);
const char *features = "";
if (program->chip_class >= GFX10 && program->wave_size == 64) {
features = "+wavefrontsize64";
}
LLVMDisasmContextRef disasm = LLVMCreateDisasmCPUFeatures("amdgcn-mesa-mesa3d",
ac_get_llvm_processor_name(program->family),
features,
&symbols, 0, NULL, NULL);
char outline[1024];
size_t pos = 0;