fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-21 18:00:13 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

anv: fix pipeline switch back for non pipelined states

Browse source 
Setting state base address can happen even before pipeline is
selected. Also we must ensure it is set to 3D for Gen12, we can't
switch back to an invalid pipeline value (UINT32_MAX).

v2: Reuse helpers (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b34422db5e ("anv: Implement Gen12 workaround for non pipelined state")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3396>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3396>
This commit is contained in:
Lionel Landwerlin 2020-01-15 00:05:30 +02:00
parent fce28a7341
commit a014105498
1 changed files with 8 additions and 13 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

21
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -40,6 +40,9 @@
#define __gen_address_offset anv_address_add #define __gen_address_offset anv_address_add
#include "common/gen_mi_builder.h" #include "common/gen_mi_builder.h"
static void genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
uint32_t pipeline);
static void static void
emit_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm) emit_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
{ {
@ -82,12 +85,8 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
* Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
* mode by putting the pipeline temporarily in 3D mode. * mode by putting the pipeline temporarily in 3D mode.
*/ */
if (cmd_buffer->state.current_pipeline != _3D) { uint32_t gen12_wa_pipeline = cmd_buffer->state.current_pipeline;
anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT), ps) { genX(flush_pipeline_select_3d)(cmd_buffer);
ps.MaskBits = 3;
ps.PipelineSelection = _3D;
}
}
#endif #endif
anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) { anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) {
@ -172,14 +171,10 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
#if GEN_GEN == 12 #if GEN_GEN == 12
/* GEN:BUG:1607854226: /* GEN:BUG:1607854226:
* *
* Put the pipeline back into compute mode. * Put the pipeline back into its current mode.
*/ */
if (cmd_buffer->state.current_pipeline != _3D) { if (gen12_wa_pipeline != UINT32_MAX)
anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT), ps) { genX(flush_pipeline_select)(cmd_buffer, gen12_wa_pipeline);
ps.MaskBits = 3;
ps.PipelineSelection = cmd_buffer->state.current_pipeline;
}
}
#endif #endif
/* After re-setting the surface state base address, we have to do some /* After re-setting the surface state base address, we have to do some