fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-16 05:00:19 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

i965/vec4: fix vertical stride to avoid breaking region parameter rule

Browse source 
From IVB PRM, vol4, part3, "General Restrictions on Regioning
Parameters":

  "If ExecSize = Width and HorzStride ≠ 0, VertStride must
   be set to Width * HorzStride."

In next patch, we are going to modify the region parameter for
uniforms and vgrf. For uniforms that are the source of
DF align1 instructions, they will have <0, 4, 1> regioning and
the execsize for those instructions will be 4, so they will break
the regioning rule. This will be the same for VGRF sources where
we use the vstride == 0 exploit.

As we know we are not going to cross the GRF boundary with that
execsize and parameters (not even with the exploit), we just fix
the vstride here.

v2:
- Move is_align1_df() (Curro)
- Refactor exec_size == width calculation (Curro)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
(cherry picked from commit 7f728bce81)
[Andres Gomez: use original is_align1_df]
Signed-off-by: Andres Gomez <agomez@igalia.com>

Conflicts:
	src/mesa/drivers/dri/i965/brw_vec4.cpp
This commit is contained in:
Samuel Iglesias Gonsálvez 2017-04-26 10:12:03 +02:00 • committed by Andres Gomez
parent 31c66e85cc
commit a013db9d1b
1 changed files with 30 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

46
src/mesa/drivers/dri/i965/brw_vec4.cpp
View file

@ -1943,6 +1943,22 @@ vec4_visitor::emit_shader_time_write(int shader_time_subindex, src_reg value)
inst->mlen = 2;
}
static bool
is_align1_df(vec4_instruction *inst)
{
switch (inst->opcode) {
case VEC4_OPCODE_FROM_DOUBLE:
case VEC4_OPCODE_TO_DOUBLE:
case VEC4_OPCODE_PICK_LOW_32BIT:
case VEC4_OPCODE_PICK_HIGH_32BIT:
case VEC4_OPCODE_SET_LOW_32BIT:
case VEC4_OPCODE_SET_HIGH_32BIT:
return true;
default:
return false;
}
}
void
vec4_visitor::convert_to_hw_regs()
{
@ -1999,6 +2015,20 @@ vec4_visitor::convert_to_hw_regs()
apply_logical_swizzle(&reg, inst, i);
src = reg;
/* From IVB PRM, vol4, part3, "General Restrictions on Regioning
* Parameters":
*
* "If ExecSize = Width and HorzStride ≠ 0, VertStride must be set
* to Width * HorzStride."
*
* We can break this rule with DF sources on DF align1
* instructions, because the exec_size would be 4 and width is 4.
* As we know we are not accessing to next GRF, it is safe to
* set vstride to the formula given by the rule itself.
*/
if (is_align1_df(inst) && (cvt(inst->exec_size) - 1) == src.width)
src.vstride = src.width + src.hstride;
}
if (inst->is_3src(devinfo)) {
@ -2245,22 +2275,6 @@ vec4_visitor::lower_simd_width()
return progress;
}
static bool
is_align1_df(vec4_instruction *inst)
{
switch (inst->opcode) {
case VEC4_OPCODE_FROM_DOUBLE:
case VEC4_OPCODE_TO_DOUBLE:
case VEC4_OPCODE_PICK_LOW_32BIT:
case VEC4_OPCODE_PICK_HIGH_32BIT:
case VEC4_OPCODE_SET_LOW_32BIT:
case VEC4_OPCODE_SET_HIGH_32BIT:
return true;
default:
return false;
}
}
static brw_predicate
scalarize_predicate(brw_predicate predicate, unsigned writemask)
{