diff --git a/src/amd/common/ac_cmdbuf.c b/src/amd/common/ac_cmdbuf.c index 3a22176256f..6774f381716 100644 --- a/src/amd/common/ac_cmdbuf.c +++ b/src/amd/common/ac_cmdbuf.c @@ -1244,6 +1244,25 @@ ac_emit_cp_acquire_mem(struct ac_cmdbuf *cs, enum amd_gfx_level gfx_level, ac_cmdbuf_end(); } +void +ac_emit_cp_atomic_mem(struct ac_cmdbuf *cs, uint32_t atomic_op, + uint32_t atomic_cmd, uint64_t va, uint64_t data, + uint64_t compare_data) +{ + ac_cmdbuf_begin(cs); + ac_cmdbuf_emit(PKT3(PKT3_ATOMIC_MEM, 7, 0)); + ac_cmdbuf_emit(ATOMIC_OP(atomic_op) | + ATOMIC_COMMAND(atomic_cmd)); + ac_cmdbuf_emit(va); /* addr lo */ + ac_cmdbuf_emit(va >> 32); /* addr hi */ + ac_cmdbuf_emit(data); /* data lo */ + ac_cmdbuf_emit(data >> 32); /* data hi */ + ac_cmdbuf_emit(compare_data); /* compare data lo */ + ac_cmdbuf_emit(compare_data >> 32); /* compare data hi */ + ac_cmdbuf_emit(10); /* loop interval */ + ac_cmdbuf_end(); +} + void ac_cmdbuf_flush_vgt_streamout(struct ac_cmdbuf *cs, enum amd_gfx_level gfx_level) { diff --git a/src/amd/common/ac_cmdbuf.h b/src/amd/common/ac_cmdbuf.h index 361a29e2bd2..f0428c0da4f 100644 --- a/src/amd/common/ac_cmdbuf.h +++ b/src/amd/common/ac_cmdbuf.h @@ -178,6 +178,11 @@ ac_emit_cp_acquire_mem(struct ac_cmdbuf *cs, enum amd_gfx_level gfx_level, enum amd_ip_type ip_type, uint32_t engine, uint32_t gcr_cntl); +void +ac_emit_cp_atomic_mem(struct ac_cmdbuf *cs, uint32_t atomic_op, + uint32_t atomic_cmd, uint64_t va, uint64_t data, + uint64_t compare_data); + void ac_cmdbuf_flush_vgt_streamout(struct ac_cmdbuf *cs, enum amd_gfx_level gfx_level); diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c index 477f2ae011d..29850aca98c 100644 --- a/src/amd/vulkan/radv_queue.c +++ b/src/amd/vulkan/radv_queue.c @@ -1514,17 +1514,7 @@ radv_create_perf_counter_lock_cs(struct radv_device *device, unsigned pass, bool if (!unlock) { uint64_t mutex_va = radv_buffer_get_va(device->perf_counter_bo) + PERF_CTR_BO_LOCK_OFFSET; - radeon_begin(cs); - radeon_emit(PKT3(PKT3_ATOMIC_MEM, 7, 0)); - radeon_emit(ATOMIC_OP(TC_OP_ATOMIC_CMPSWAP_32) | ATOMIC_COMMAND(ATOMIC_COMMAND_LOOP)); - radeon_emit(mutex_va); /* addr lo */ - radeon_emit(mutex_va >> 32); /* addr hi */ - radeon_emit(1); /* data lo */ - radeon_emit(0); /* data hi */ - radeon_emit(0); /* compare data lo */ - radeon_emit(0); /* compare data hi */ - radeon_emit(10); /* loop interval */ - radeon_end(); + ac_emit_cp_atomic_mem(cs->b, TC_OP_ATOMIC_CMPSWAP_32, ATOMIC_COMMAND_LOOP, mutex_va, 1, 0); } uint64_t va = radv_buffer_get_va(device->perf_counter_bo) + PERF_CTR_BO_PASS_OFFSET;