From a010c2694a09f75facda76e9ebe20168f004b822 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 5 Feb 2026 12:09:56 +0100 Subject: [PATCH] radv: move {depth,stencil}_compress_disable to the image view extra info Doesn't have to be a pipeline parameter. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/meta/radv_meta_decompress.c | 44 ++++++++++------------ src/amd/vulkan/radv_cmd_buffer.c | 14 +------ src/amd/vulkan/radv_cmd_buffer.h | 1 - src/amd/vulkan/radv_image_view.c | 18 +++++++-- src/amd/vulkan/radv_image_view.h | 2 + src/amd/vulkan/radv_pipeline_graphics.c | 5 --- src/amd/vulkan/radv_pipeline_graphics.h | 3 -- 7 files changed, 37 insertions(+), 50 deletions(-) diff --git a/src/amd/vulkan/meta/radv_meta_decompress.c b/src/amd/vulkan/meta/radv_meta_decompress.c index 6230fcc2d3d..e03a9d1aa1d 100644 --- a/src/amd/vulkan/meta/radv_meta_decompress.c +++ b/src/amd/vulkan/meta/radv_meta_decompress.c @@ -46,15 +46,8 @@ get_pipeline_gfx(struct radv_device *device, struct radv_image *image, VkPipelin .sampleLocationsEnable = false, }; - const VkGraphicsPipelineCreateInfoRADV radv_info = { - .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO_RADV, - .depth_compress_disable = true, - .stencil_compress_disable = true, - }; - const VkGraphicsPipelineCreateInfo pipeline_create_info = { .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO, - .pNext = &radv_info, .stageCount = 2, .pStages = (VkPipelineShaderStageCreateInfo[]){ @@ -167,24 +160,25 @@ radv_process_depth_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_i .usage = VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT, }; - radv_image_view_init(&iview, device, - &(VkImageViewCreateInfo){ - .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO, - .pNext = &iview_usage_info, - .flags = VK_IMAGE_VIEW_CREATE_DRIVER_INTERNAL_BIT_MESA, - .image = radv_image_to_handle(image), - .viewType = radv_meta_get_view_type(image), - .format = image->vk.format, - .subresourceRange = - { - .aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT, - .baseMipLevel = range->baseMipLevel + level, - .levelCount = 1, - .baseArrayLayer = range->baseArrayLayer + layer, - .layerCount = 1, - }, - }, - NULL); + radv_image_view_init( + &iview, device, + &(VkImageViewCreateInfo){ + .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO, + .pNext = &iview_usage_info, + .flags = VK_IMAGE_VIEW_CREATE_DRIVER_INTERNAL_BIT_MESA, + .image = radv_image_to_handle(image), + .viewType = radv_meta_get_view_type(image), + .format = image->vk.format, + .subresourceRange = + { + .aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT, + .baseMipLevel = range->baseMipLevel + level, + .levelCount = 1, + .baseArrayLayer = range->baseArrayLayer + layer, + .layerCount = 1, + }, + }, + &(struct radv_image_view_extra_create_info){.depth_compress_disable = true, .stencil_compress_disable = true}); const VkRenderingAttachmentInfo depth_att = { .sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO, diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index a54d8d0d1d8..e1038f34f57 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -4713,7 +4713,7 @@ radv_gfx11_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, const struct rad { const struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - uint32_t db_render_control = ds->db_render_control | cmd_buffer->state.db_render_control; + uint32_t db_render_control = ds->db_render_control; struct radv_cmd_stream *cs = cmd_buffer->cs; if (!depth_compressed) @@ -4774,7 +4774,7 @@ radv_gfx6_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, const struct radv const struct radv_physical_device *pdev = radv_device_physical(device); uint64_t db_htile_data_base = ds->ac.u.gfx6.db_htile_data_base; uint32_t db_htile_surface = ds->ac.u.gfx6.db_htile_surface; - uint32_t db_render_control = ds->db_render_control | cmd_buffer->state.db_render_control; + uint32_t db_render_control = ds->db_render_control; uint32_t db_z_info = ds->ac.db_z_info; if (!depth_compressed) @@ -8819,11 +8819,6 @@ radv_bind_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_grap radv_bind_custom_blend_mode(cmd_buffer, graphics_pipeline->custom_blend_mode); - if (cmd_buffer->state.db_render_control != graphics_pipeline->db_render_control) { - cmd_buffer->state.db_render_control = graphics_pipeline->db_render_control; - cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER; - } - if (cmd_buffer->state.uses_out_of_order_rast != graphics_pipeline->uses_out_of_order_rast || cmd_buffer->state.uses_vrs_attachment != graphics_pipeline->uses_vrs_attachment) { cmd_buffer->state.uses_out_of_order_rast = graphics_pipeline->uses_out_of_order_rast; @@ -15497,11 +15492,6 @@ radv_reset_pipeline_state(struct radv_cmd_buffer *cmd_buffer, VkPipelineBindPoin if (cmd_buffer->state.emitted_graphics_pipeline) { radv_bind_custom_blend_mode(cmd_buffer, 0); - if (cmd_buffer->state.db_render_control) { - cmd_buffer->state.db_render_control = 0; - cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER; - } - if (cmd_buffer->state.spi_shader_col_format || cmd_buffer->state.spi_shader_z_format || cmd_buffer->state.cb_shader_mask) { cmd_buffer->state.spi_shader_col_format = 0; diff --git a/src/amd/vulkan/radv_cmd_buffer.h b/src/amd/vulkan/radv_cmd_buffer.h index 9e5bbfc44d6..2b6402251db 100644 --- a/src/amd/vulkan/radv_cmd_buffer.h +++ b/src/amd/vulkan/radv_cmd_buffer.h @@ -413,7 +413,6 @@ struct radv_cmd_state { /* Custom blend mode for internal operations. */ unsigned custom_blend_mode; - unsigned db_render_control; unsigned last_cb_target_mask; diff --git a/src/amd/vulkan/radv_image_view.c b/src/amd/vulkan/radv_image_view.c index 5a871e95df3..b6aaf1ef6dc 100644 --- a/src/amd/vulkan/radv_image_view.c +++ b/src/amd/vulkan/radv_image_view.c @@ -556,7 +556,8 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff static void radv_initialise_ds_surface(const struct radv_device *device, struct radv_ds_buffer_info *ds, - struct radv_image_view *iview, VkImageAspectFlags ds_aspects) + struct radv_image_view *iview, VkImageAspectFlags ds_aspects, bool depth_compress_disable, + bool stencil_compress_disable) { const struct radv_physical_device *pdev = radv_device_physical(device); unsigned level = iview->vk.base_mip_level; @@ -606,6 +607,10 @@ radv_initialise_ds_surface(const struct radv_device *device, struct radv_ds_buff if (pdev->info.gfx_level >= GFX11) { radv_gfx11_set_db_render_control(device, iview->image->vk.samples, &ds->db_render_control); } + + /* For depth/stencil expand on graphics. */ + ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(depth_compress_disable) | + S_028000_STENCIL_COMPRESS_DISABLE(stencil_compress_disable); } void @@ -774,6 +779,8 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device, iview->disable_dcc_mrt = extra_create_info ? extra_create_info->disable_dcc_mrt : false; iview->disable_tc_compat_cmask_mrt = extra_create_info ? extra_create_info->disable_tc_compat_cmask_mrt : false; + const bool depth_compress_disable = extra_create_info ? extra_create_info->depth_compress_disable : false; + const bool stencil_compress_disable = extra_create_info ? extra_create_info->stencil_compress_disable : false; bool disable_compression = extra_create_info ? extra_create_info->disable_compression : false; bool enable_compression = extra_create_info ? extra_create_info->enable_compression : false; for (unsigned i = 0; i < plane_count; ++i) { @@ -790,11 +797,14 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device, if (iview->vk.usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT) { if (vk_format_has_depth(image->vk.format) && vk_format_has_stencil(image->vk.format)) radv_initialise_ds_surface(device, &iview->depth_stencil_desc, iview, - VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT); + VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT, depth_compress_disable, + stencil_compress_disable); if (vk_format_has_depth(image->vk.format)) - radv_initialise_ds_surface(device, &iview->depth_only_desc, iview, VK_IMAGE_ASPECT_DEPTH_BIT); + radv_initialise_ds_surface(device, &iview->depth_only_desc, iview, VK_IMAGE_ASPECT_DEPTH_BIT, + depth_compress_disable, stencil_compress_disable); if (vk_format_has_stencil(image->vk.format)) - radv_initialise_ds_surface(device, &iview->stencil_only_desc, iview, VK_IMAGE_ASPECT_STENCIL_BIT); + radv_initialise_ds_surface(device, &iview->stencil_only_desc, iview, VK_IMAGE_ASPECT_STENCIL_BIT, + depth_compress_disable, stencil_compress_disable); } } diff --git a/src/amd/vulkan/radv_image_view.h b/src/amd/vulkan/radv_image_view.h index ef26550551a..2ad6b7f69e6 100644 --- a/src/amd/vulkan/radv_image_view.h +++ b/src/amd/vulkan/radv_image_view.h @@ -77,6 +77,8 @@ struct radv_image_view_extra_create_info { bool enable_compression; bool disable_dcc_mrt; bool disable_tc_compat_cmask_mrt; + bool depth_compress_disable; + bool stencil_compress_disable; bool from_client; /**< Set only if this came from vkCreateImage */ }; diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index de84c948e6b..6610c22fb47 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -3352,11 +3352,6 @@ radv_pipeline_init_extra(struct radv_graphics_pipeline *pipeline, const VkGraphi const struct vk_graphics_pipeline_state *state) { pipeline->custom_blend_mode = radv_info->custom_blend_mode; - - if (radv_pipeline_has_ds_attachments(state->rp)) { - pipeline->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(radv_info->depth_compress_disable); - pipeline->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(radv_info->stencil_compress_disable); - } } bool diff --git a/src/amd/vulkan/radv_pipeline_graphics.h b/src/amd/vulkan/radv_pipeline_graphics.h index 4fb1c09f75b..77a5a97aec2 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.h +++ b/src/amd/vulkan/radv_pipeline_graphics.h @@ -28,8 +28,6 @@ typedef struct VkGraphicsPipelineCreateInfoRADV { VkStructureType sType; const void *pNext; - VkBool32 depth_compress_disable; - VkBool32 stencil_compress_disable; uint32_t custom_blend_mode; } VkGraphicsPipelineCreateInfoRADV; @@ -139,7 +137,6 @@ struct radv_graphics_pipeline { struct radv_multisample_state ms; struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param; - uint32_t db_render_control; /* Last pre-PS API stage */ mesa_shader_stage last_vgt_api_stage;