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r600/sfn: Set minimum required registers based on array allocation

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In the rare case that after register allocation the highest directly
accessed register index is below the highest value used for an
indirectly accessed array we have to ensure that the shader allocates
enough registers to account for these indices that are not seen by the
assembler.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7966
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20451>
This commit is contained in:
Gert Wollny 2022-12-29 11:56:38 +01:00 • committed by Marge Bot
parent 8348c9c84d
commit 9fd9f3cd10
3 changed files with 9 additions and 3 deletions
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2
src/gallium/drivers/r600/sfn/sfn_nir.cpp
View file

@ -1029,11 +1029,13 @@ r600_shader_from_nir(struct r600_context *rctx,
rscreen->b.family,
rscreen->has_compressed_msaa_texturing);
r600::sfn_log << r600::SfnLog::shader_info << "pipeshader->shader.processor_type = "
<< pipeshader->shader.processor_type << "\n";
pipeshader->shader.bc.type = pipeshader->shader.processor_type;
pipeshader->shader.bc.isa = rctx->isa;
pipeshader->shader.bc.ngpr = shader->required_registers();
r600::Assembler afs(&pipeshader->shader, *key);
if (!afs.lower(scheduled_shader)) {

1
src/gallium/drivers/r600/sfn/sfn_shader.cpp
View file

@ -520,6 +520,7 @@ Shader::allocate_local_registers(const exec_list *registers)
{
if (value_factory().allocate_registers(registers))
m_indirect_files |= 1 << TGSI_FILE_TEMPORARY;
m_required_registers = value_factory().next_register_index() - 1;
}
bool

9
src/gallium/drivers/r600/sfn/sfn_shader.h
View file

@ -189,8 +189,8 @@ public:
void set_info(nir_shader *nir);
void get_shader_info(r600_shader *sh_info);
r600_chip_class chip_class() const { return m_chip_class; };
void set_chip_class(r600_chip_class cls) { m_chip_class = cls; };
r600_chip_class chip_class() const { return m_chip_class; }
void set_chip_class(r600_chip_class cls) { m_chip_class = cls; }
void start_new_block(int nesting_depth);
@ -205,7 +205,7 @@ public:
void chain_scratch_read(Instr *instr);
void chain_ssbo_read(Instr *instr);
virtual uint32_t enabled_stream_buffers_mask() const { return 0; };
virtual uint32_t enabled_stream_buffers_mask() const { return 0; }
size_t noutputs() const { return m_outputs.size(); }
size_t ninputs() const { return m_inputs.size(); }
@ -245,6 +245,8 @@ public:
virtual unsigned image_size_const_offset() { return 0;}
auto required_registers() const { return m_required_registers;}
protected:
enum ESlots {
es_face,
@ -350,6 +352,7 @@ private:
int32_t m_ssbo_image_offset{0};
uint32_t m_nloops{0};
uint32_t m_required_registers{0};
class InstructionChain : public InstrVisitor {
public: