From 9fb2c84768c30702fd8177b81ec0bb45c110bdd7 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Fri, 24 Sep 2021 13:28:05 +0300 Subject: [PATCH] isl: only bump the min row pitch for display when not specified If the ISL caller didn't specify a row_pitch_B, let's use the NVIDIA/AMD requirements. Otherwise keep using the Intel requirement, as the caller is likely trying to import a buffer and if we can deal with that row_pitch_B, we should accept it. Signed-off-by: Lionel Landwerlin Fixes: a3a4517f4147a0 ("isl: Work around NVIDIA and AMD display pitch requirements") Reported-by: Dongwon Kim Reviewed-by: Nanley Chery Part-of: --- src/intel/isl/isl.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 0daba4bbbfe..8844db965ad 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -1581,10 +1581,20 @@ isl_calc_row_pitch_alignment(const struct isl_device *dev, * "When using linear memory, this must be at least 64 byte aligned." * * However, when displaying on NVIDIA and recent AMD GPUs via PRIME, - * we need a larger pitch of 256 bytes. We do that just in case. + * we need a larger pitch of 256 bytes. + * + * If the ISL caller didn't specify a row_pitch_B, then we should assume + * the NVIDIA/AMD requirements. Otherwise, if we have a specified + * row_pitch_B, this is probably because the caller is trying to import a + * buffer. In that case we limit the minimum row pitch to the Intel HW + * requirement. */ - if (surf_info->usage & ISL_SURF_USAGE_DISPLAY_BIT) - alignment = isl_align(alignment, 256); + if (surf_info->usage & ISL_SURF_USAGE_DISPLAY_BIT) { + if (surf_info->row_pitch_B == 0) + alignment = isl_align(alignment, 256); + else + alignment = isl_align(alignment, 64); + } return alignment; }