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panfrost: Implement pan_tiler for non-hierarchy GPUs
The algorithm is as described. Nothing fancy here, just need to add some new code paths depending on which model we're running on. Tomeu: - Also disable tiling when !hierarchy and !vertex_count - Avoid creating polygon lists smaller than the minimum when vertex_count > 0 but tile size smaller than 16 byte - Take into account tile size when calculating polygon list size for !hierarchy - Allow 0-sized tiles in a single dimension Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
This commit is contained in:
Alyssa Rosenzweig
Tomeu Vizoso
parent
63cd5b8198
commit
9fb0904712
6 changed files with 106 additions and 136 deletions
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@ -59,24 +59,25 @@ static struct midgard_tiler_descriptor
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panfrost_emit_midg_tiler(struct panfrost_batch *batch, unsigned vertex_count)
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{
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struct panfrost_screen *screen = pan_screen(batch->ctx->base.screen);
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bool hierarchy = !(screen->quirks & MIDGARD_NO_HIER_TILING);
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struct midgard_tiler_descriptor t = {0};
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unsigned height = batch->key.height;
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unsigned width = batch->key.width;
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t.hierarchy_mask =
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panfrost_choose_hierarchy_mask(width, height, vertex_count);
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panfrost_choose_hierarchy_mask(width, height, vertex_count, hierarchy);
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/* Compute the polygon header size and use that to offset the body */
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unsigned header_size = panfrost_tiler_header_size(
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width, height, t.hierarchy_mask);
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width, height, t.hierarchy_mask, hierarchy);
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t.polygon_list_size = panfrost_tiler_full_size(
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width, height, t.hierarchy_mask);
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width, height, t.hierarchy_mask, hierarchy);
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/* Sanity check */
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if (t.hierarchy_mask) {
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if (vertex_count) {
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struct panfrost_bo *tiler_heap;
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tiler_heap = panfrost_batch_get_tiler_heap(batch);
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@ -92,6 +93,7 @@ panfrost_emit_midg_tiler(struct panfrost_batch *batch, unsigned vertex_count)
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struct panfrost_bo *tiler_dummy;
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tiler_dummy = panfrost_batch_get_tiler_dummy(batch);
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header_size = MALI_TILER_MINIMUM_HEADER_SIZE;
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/* The tiler is disabled, so don't allow the tiler heap */
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t.heap_start = tiler_dummy->gpu;
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@ -101,11 +103,11 @@ panfrost_emit_midg_tiler(struct panfrost_batch *batch, unsigned vertex_count)
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t.polygon_list = tiler_dummy->gpu;
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/* Disable the tiler */
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t.hierarchy_mask |= MALI_TILER_DISABLED;
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if (screen->quirks & MIDGARD_SFBD) {
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t.hierarchy_mask = 0xFFF; /* TODO: What's this? */
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t.polygon_list_size = 0x200;
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if (hierarchy)
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t.hierarchy_mask |= MALI_TILER_DISABLED;
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else {
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t.hierarchy_mask = MALI_TILER_USER;
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t.polygon_list_size = MALI_TILER_MINIMUM_HEADER_SIZE + 4;
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/* We don't have a SET_VALUE job, so write the polygon list manually */
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uint32_t *polygon_list_body = (uint32_t *) (tiler_dummy->cpu + header_size);
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@ -302,7 +302,8 @@ panfrost_scoreboard_set_value(struct panfrost_batch *batch)
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/* Okay, we do. Let's generate it. We'll need the job's polygon list
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* regardless of size. */
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mali_ptr polygon_list = panfrost_batch_get_polygon_list(batch, 0);
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mali_ptr polygon_list = panfrost_batch_get_polygon_list(batch,
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MALI_TILER_MINIMUM_HEADER_SIZE);
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struct panfrost_transfer job =
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panfrost_set_value_job(batch, polygon_list);
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@ -56,14 +56,14 @@ panfrost_pack_work_groups_fused(
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/* Tiler structure size computation */
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unsigned
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panfrost_tiler_header_size(unsigned width, unsigned height, unsigned mask);
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panfrost_tiler_header_size(unsigned width, unsigned height, unsigned mask, bool hierarchy);
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unsigned
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panfrost_tiler_full_size(unsigned width, unsigned height, unsigned mask);
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panfrost_tiler_full_size(unsigned width, unsigned height, unsigned mask, bool hierarchy);
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unsigned
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panfrost_choose_hierarchy_mask(
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unsigned width, unsigned height,
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unsigned vertex_count);
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unsigned vertex_count, bool hierarchy);
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#endif
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@ -218,13 +218,6 @@
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/* Likewise, each tile per level has 512 bytes of body */
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#define FULL_BYTES_PER_TILE 0x200
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/* Absent any geometry, the minimum size of the header */
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#define MINIMUM_HEADER_SIZE 0x200
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/* Mask of valid hierarchy levels: one bit for each level from min...max
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* inclusive */
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#define HIERARCHY_MASK (((MAX_TILE_SIZE / MIN_TILE_SIZE) << 1) - 1)
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/* If the width-x-height framebuffer is divided into tile_size-x-tile_size
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* tiles, how many tiles are there? Rounding up in each direction. For the
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* special case of tile_size=16, this aligns with the usual Midgard count.
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@ -233,108 +226,86 @@
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* a a fixed-tile size (not any of a number of power-of-twos) */
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static unsigned
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pan_tile_count(unsigned width, unsigned height, unsigned tile_size)
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pan_tile_count(unsigned width, unsigned height, unsigned tile_width, unsigned tile_height)
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{
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unsigned aligned_width = ALIGN_POT(width, tile_size);
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unsigned aligned_height = ALIGN_POT(height, tile_size);
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unsigned aligned_width = ALIGN_POT(width, tile_width);
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unsigned aligned_height = ALIGN_POT(height, tile_height);
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unsigned tile_count_x = aligned_width / tile_size;
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unsigned tile_count_y = aligned_height / tile_size;
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unsigned tile_count_x = aligned_width / tile_width;
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unsigned tile_count_y = aligned_height / tile_height;
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return tile_count_x * tile_count_y;
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}
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/* For `masked_count` of the smallest tile sizes masked out, computes how the
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* size of the polygon list header. We iterate the tile sizes (16x16 through
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* 2048x2048, if nothing is masked; (16*2^masked_count)x(16*2^masked_count)
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* through 2048x2048 more generally. For each tile size, we figure out how many
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* tiles there are at this hierarchy level and therefore many bytes this level
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* is, leaving us with a byte count for each level. We then just sum up the
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* byte counts across the levels to find a byte count for all levels. */
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* 2048x2048). For each tile size, we figure out how many tiles there are at
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* this hierarchy level and therefore many bytes this level is, leaving us with
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* a byte count for each level. We then just sum up the byte counts across the
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* levels to find a byte count for all levels. */
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static unsigned
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panfrost_raw_segment_size(
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panfrost_hierarchy_size(
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unsigned width,
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unsigned height,
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unsigned masked_count,
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unsigned end_level,
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unsigned mask,
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unsigned bytes_per_tile)
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{
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unsigned size = PROLOGUE_SIZE;
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/* Normally we start at 16x16 tiles (MIN_TILE_SHIFT), but we add more
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* if anything is masked off */
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/* Iterate hierarchy levels */
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unsigned start_level = MIN_TILE_SHIFT + masked_count;
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for (unsigned b = 0; b < (MAX_TILE_SHIFT - MIN_TILE_SHIFT); ++b) {
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/* Check if this level is enabled */
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if (!(mask & (1 << b)))
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continue;
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/* Iterate hierarchy levels / tile sizes */
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for (unsigned i = start_level; i <= end_level; ++i) {
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/* Shift from a level to a tile size */
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unsigned tile_size = (1 << i);
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unsigned tile_size = (1 << b) * MIN_TILE_SIZE;
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unsigned tile_count = pan_tile_count(width, height, tile_size);
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unsigned tile_count = pan_tile_count(width, height, tile_size, tile_size);
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unsigned level_count = bytes_per_tile * tile_count;
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size += level_count;
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}
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/* This size will be used as an offset, so ensure it's aligned */
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return ALIGN_POT(size, 512);
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return ALIGN_POT(size, 0x200);
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}
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/* Given a hierarchy mask and a framebuffer size, compute the size of one of
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* the segments (header or body) */
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/* Implement the formula:
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*
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* 0x200 + bytes_per_tile * ceil(W / w) * ceil(H / h)
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*
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* rounding down the answer to the nearest 0x200. This is used to compute both
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* header and body sizes for GPUs without hierarchical tiling. Essentially,
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* computing a single hierarchy level, since there isn't any hierarchy!
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*/
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static unsigned
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panfrost_segment_size(
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unsigned width, unsigned height,
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unsigned mask, unsigned bytes_per_tile)
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panfrost_flat_size(unsigned width, unsigned height, unsigned dim, unsigned bytes_per_tile)
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{
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/* The tiler-disabled case should have been handled by the caller */
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assert(mask);
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/* First, extract the tile dimensions */
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/* Some levels are enabled. Ensure that only smaller levels are
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* disabled and there are no gaps. Theoretically the hardware is more
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* flexible, but there's no known reason to use other configurations
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* and this keeps the code simple. Since we know the 0x80 or 0x100 bit
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* is set, ctz(mask) will return the number of masked off levels. */
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unsigned tw = (1 << (dim & 0b111)) * 8;
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unsigned th = (1 << ((dim & (0b111 << 6)) >> 6)) * 8;
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unsigned masked_count = __builtin_ctz(mask);
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/* tile_count is ceil(W/w) * ceil(H/h) */
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unsigned raw = pan_tile_count(width, height, tw, th) * bytes_per_tile;
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assert(mask & (0x80 | 0x100));
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assert(((mask >> masked_count) & ((mask >> masked_count) + 1)) == 0);
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/* Figure out the top level */
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unsigned unused_count = __builtin_clz(mask);
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unsigned top_bit = ((8 * sizeof(mask)) - 1) - unused_count;
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/* We don't have bits for nonexistant levels below 16x16 */
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unsigned top_level = top_bit + 4;
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/* Everything looks good. Use the number of trailing zeroes we found to
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* figure out how many smaller levels are disabled to compute the
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* actual header size */
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return panfrost_raw_segment_size(width, height,
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masked_count, top_level, bytes_per_tile);
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/* Round down and add offset */
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return 0x200 + ((raw / 0x200) * 0x200);
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}
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/* Given a hierarchy mask and a framebuffer size, compute the header size */
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unsigned
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panfrost_tiler_header_size(unsigned width, unsigned height, unsigned mask)
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panfrost_tiler_header_size(unsigned width, unsigned height, unsigned mask, bool hierarchy)
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{
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mask &= HIERARCHY_MASK;
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/* If no hierarchy levels are enabled, that means there is no geometry
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* for the tiler to process, so use a minimum size. Used for clears */
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if (mask == 0x00)
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return MINIMUM_HEADER_SIZE;
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return panfrost_segment_size(width, height, mask, HEADER_BYTES_PER_TILE);
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if (hierarchy)
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return panfrost_hierarchy_size(width, height, mask, HEADER_BYTES_PER_TILE);
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else
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return panfrost_flat_size(width, height, mask, HEADER_BYTES_PER_TILE);
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}
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/* The combined header/body is sized similarly (but it is significantly
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@ -343,14 +314,38 @@ panfrost_tiler_header_size(unsigned width, unsigned height, unsigned mask)
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*/
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unsigned
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panfrost_tiler_full_size(unsigned width, unsigned height, unsigned mask)
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panfrost_tiler_full_size(unsigned width, unsigned height, unsigned mask, bool hierarchy)
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{
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mask &= HIERARCHY_MASK;
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if (hierarchy)
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return panfrost_hierarchy_size(width, height, mask, FULL_BYTES_PER_TILE);
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else
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return panfrost_flat_size(width, height, mask, FULL_BYTES_PER_TILE);
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}
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if (mask == 0x00)
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return MINIMUM_HEADER_SIZE;
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/* On GPUs without hierarchical tiling, we choose a tile size directly and
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* stuff it into the field otherwise known as hierarchy mask (not a mask). */
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return panfrost_segment_size(width, height, mask, FULL_BYTES_PER_TILE);
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static unsigned
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panfrost_choose_tile_size(
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unsigned width, unsigned height, unsigned vertex_count)
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{
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/* Figure out the ideal tile size. Eventually a heuristic should be
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* used for this */
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unsigned best_w = 16;
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unsigned best_h = 16;
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/* Clamp so there are less than 64 tiles in each direction */
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best_w = MAX2(best_w, util_next_power_of_two(width / 63));
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best_h = MAX2(best_h, util_next_power_of_two(height / 63));
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/* We have our ideal tile size, so encode */
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unsigned exp_w = util_logbase2(best_w / 16);
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unsigned exp_h = util_logbase2(best_h / 16);
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return exp_w | (exp_h << 6);
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}
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/* In the future, a heuristic to choose a tiler hierarchy mask would go here.
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@ -362,13 +357,16 @@ panfrost_tiler_full_size(unsigned width, unsigned height, unsigned mask)
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unsigned
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panfrost_choose_hierarchy_mask(
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unsigned width, unsigned height,
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unsigned vertex_count)
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unsigned vertex_count, bool hierarchy)
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{
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/* If there is no geometry, we don't bother enabling anything */
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if (!vertex_count)
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return 0x00;
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if (!hierarchy)
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return panfrost_choose_tile_size(width, height, vertex_count);
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/* Otherwise, default everything on. TODO: Proper tests */
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return 0xFF;
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@ -1392,9 +1392,17 @@ struct mali_payload_fragment {
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/* See pan_tiler.c for derivation */
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#define MALI_HIERARCHY_MASK ((1 << 9) - 1)
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/* Flag disabling the tiler for clear-only jobs */
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/* Flag disabling the tiler for clear-only jobs, with
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hierarchical tiling */
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#define MALI_TILER_DISABLED (1 << 12)
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/* Flag selecting userspace-generated polygon list, for clear-only jobs without
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* hierarhical tiling. */
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#define MALI_TILER_USER 0xFFF
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/* Absent any geometry, the minimum size of the polygon list header */
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#define MALI_TILER_MINIMUM_HEADER_SIZE 0x200
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struct midgard_tiler_descriptor {
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/* Size of the entire polygon list; see pan_tiler.c for the
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* computation. It's based on hierarchical tiling */
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@ -513,7 +513,8 @@ pandecode_midgard_tiler_descriptor(
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const struct midgard_tiler_descriptor *t,
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unsigned width,
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unsigned height,
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bool is_fragment)
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bool is_fragment,
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bool has_hierarchy)
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{
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pandecode_log(".tiler = {\n");
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pandecode_indent++;
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@ -546,8 +547,8 @@ pandecode_midgard_tiler_descriptor(
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/* Now that we've sanity checked, we'll try to calculate the sizes
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* ourselves for comparison */
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unsigned ref_header = panfrost_tiler_header_size(width, height, t->hierarchy_mask);
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unsigned ref_size = panfrost_tiler_full_size(width, height, t->hierarchy_mask);
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unsigned ref_header = panfrost_tiler_header_size(width, height, t->hierarchy_mask, has_hierarchy);
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unsigned ref_size = panfrost_tiler_full_size(width, height, t->hierarchy_mask, has_hierarchy);
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if (!((ref_header == body_offset) && (ref_size == t->polygon_list_size))) {
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pandecode_msg("XXX: bad polygon list size (expected %d / 0x%x)\n",
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@ -630,44 +631,6 @@ pandecode_midgard_tiler_descriptor(
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pandecode_log("}\n");
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}
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static void
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pandecode_midgard_tiler_descriptor_0x20(
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const struct midgard_tiler_descriptor *t)
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{
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pandecode_log(".tiler = {\n");
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pandecode_indent++;
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pandecode_prop("hierarchy_mask = 0x%" PRIx16, t->hierarchy_mask);
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pandecode_prop("flags = 0x%" PRIx16, t->flags);
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MEMORY_PROP(t, polygon_list);
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MEMORY_PROP(t, polygon_list_body);
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pandecode_prop("polygon_list_size = 0x%x", t->polygon_list_size);
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MEMORY_PROP(t, heap_start);
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MEMORY_PROP(t, heap_end);
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/* We've never seen weights used in practice, but we know from the
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* kernel these fields are there */
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bool nonzero_weights = false;
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for (unsigned w = 0; w < ARRAY_SIZE(t->weights); ++w) {
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nonzero_weights |= t->weights[w] != 0x0;
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}
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if (nonzero_weights) {
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pandecode_log(".weights = {");
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for (unsigned w = 0; w < ARRAY_SIZE(t->weights); ++w) {
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pandecode_log("%d, ", t->weights[w]);
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}
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pandecode_log("},");
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}
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pandecode_indent--;
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pandecode_log("}\n");
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}
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/* Information about the framebuffer passed back for
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* additional analysis */
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@ -792,11 +755,9 @@ pandecode_sfbd(uint64_t gpu_va, int job_no, bool is_fragment, unsigned gpu_id)
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MEMORY_PROP(s, unknown_address_0);
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const struct midgard_tiler_descriptor t = s->tiler;
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if (gpu_id == 0x0720 || gpu_id == 0x0820 || gpu_id == 0x0830)
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/* These ones don't have an "Advanced Tiling Unit" */
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pandecode_midgard_tiler_descriptor_0x20(&t);
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else
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pandecode_midgard_tiler_descriptor(&t, s->width + 1, s->height + 1, is_fragment);
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bool has_hierarchy = !(gpu_id == 0x0720 || gpu_id == 0x0820 || gpu_id == 0x0830);
|
||||
pandecode_midgard_tiler_descriptor(&t, s->width + 1, s->height + 1, is_fragment, has_hierarchy);
|
||||
|
||||
pandecode_indent--;
|
||||
pandecode_log("};\n");
|
||||
|
|
@ -1157,7 +1118,7 @@ pandecode_mfbd_bfr(uint64_t gpu_va, int job_no, bool is_fragment)
|
|||
pandecode_prop("unknown2 = 0x%x", fb->unknown2);
|
||||
MEMORY_PROP(fb, scratchpad);
|
||||
const struct midgard_tiler_descriptor t = fb->tiler;
|
||||
pandecode_midgard_tiler_descriptor(&t, fb->width1 + 1, fb->height1 + 1, is_fragment);
|
||||
pandecode_midgard_tiler_descriptor(&t, fb->width1 + 1, fb->height1 + 1, is_fragment, true);
|
||||
|
||||
if (fb->zero3 || fb->zero4) {
|
||||
pandecode_msg("XXX: framebuffer zeros tripped\n");
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue