diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index bfffb166e97..7adec6f7381 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1525,6 +1525,24 @@ static void ac_copy_dcc_equation(const struct radeon_info *info,
    }
 }
 
+static void ac_copy_htile_equation(const struct radeon_info *info,
+                                   ADDR2_COMPUTE_HTILE_INFO_OUTPUT *htile,
+                                   struct gfx9_meta_equation *equation)
+{
+   equation->meta_block_width = htile->metaBlkWidth;
+   equation->meta_block_height = htile->metaBlkHeight;
+
+   /* gfx9_meta_equation doesn't store the first 8 and the last 4 elements. They must be 0. */
+   for (unsigned i = 0; i < 8; i++)
+      assert(htile->equation.gfx10_bits[i] == 0);
+
+   for (unsigned i = ARRAY_SIZE(equation->u.gfx10_bits) + 8; i < 72; i++)
+      assert(htile->equation.gfx10_bits[i] == 0);
+
+   memcpy(equation->u.gfx10_bits, htile->equation.gfx10_bits + 8,
+          sizeof(equation->u.gfx10_bits));
+}
+
 static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_info *info,
                                 const struct ac_surf_config *config, struct radeon_surf *surf,
                                 bool compressed, ADDR2_COMPUTE_SURFACE_INFO_INPUT *in)
@@ -1668,6 +1686,8 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
       if (!surf->num_meta_levels)
          surf->meta_size = 0;
 
+      if (info->chip_class >= GFX10)
+         ac_copy_htile_equation(info, &hout, &surf->u.gfx9.zs.htile_equation);
       return 0;
    }
 
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 2852f171fc5..75ae433fb40 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -173,16 +173,19 @@ struct gfx9_surf_level {
 /**
  * Meta address equation.
  *
+ * DCC/HTILE address equation for doing DCC/HTILE address computations in shaders.
+ *
+ * ac_surface_meta_address_test.c contains the reference implementation.
+ * ac_nir_{dcc,htile}_addr_from_coord is the NIR implementation.
+ *
  * For DCC:
- *
- * DCC address equation for doing DCC address computations in shaders.
- *
- * ac_surface_dcc_address_test.c contains the reference implementation.
- * ac_nir_dcc_addr_from_coord is the NIR implementation.
- *
  * The gfx9 equation doesn't support mipmapping.
  * The gfx10 equation doesn't support mipmapping and MSAA.
  * (those are also limitations of Addr2ComputeDccAddrFromCoord)
+ *
+ * For HTILE:
+ * The gfx9 equation isn't implemented.
+ * The gfx10 equation doesn't support mipmapping.
  */
 struct gfx9_meta_equation {
    uint16_t meta_block_width;
@@ -213,6 +216,8 @@ struct gfx9_meta_equation {
       /* The gfx10 DCC equation is chip-specific, it requires 64KB_R_X, and it varies with:
        * - bpp
        * - pipe_aligned
+       *
+       * The gfx10 HTILE equation is chip-specific.
        */
       uint16_t gfx10_bits[60];
    } u;
@@ -285,6 +290,9 @@ struct gfx9_surf_layout {
          uint64_t stencil_offset; /* separate stencil */
          uint16_t stencil_epitch;   /* gfx9 only, not on gfx10 */
          uint8_t stencil_swizzle_mode;
+
+         /* For HTILE VRS. */
+         struct gfx9_meta_equation htile_equation;
       } zs;
    };
 };