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nvc0/ir: Teach insnCanLoad about double immediates

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Teach insnCanLoad about double immediates, together with the
"Add support for merge-s to the ConstantFolding pass"

This turns the following (nvc0) code:
  1: mov u32 $r2 0x00000000 (8)
  2: mov u32 $r3 0x3fe00000 (8)
  3: add f64 $r0d $r0d $r2d (8)

Into:
  1: add f64 $r0d $r0d 0.500000 (8)

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
This commit is contained in:
Hans de Goede 2015-11-05 14:32:37 +01:00 • committed by Ilia Mirkin
parent 428506ece2
commit 9f2f8bda6e
1 changed files with 19 additions and 6 deletions
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25
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
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@ -338,17 +338,30 @@ TargetNVC0::insnCanLoad(const Instruction *i, int s,
if (sf == FILE_IMMEDIATE) {
Storage &reg = ld->getSrc(0)->asImm()->reg;
if (typeSizeof(i->sType) > 4)
return false;
if (opInfo[i->op].immdBits != 0xffffffff) {
if (i->sType == TYPE_F32) {
if (opInfo[i->op].immdBits != 0xffffffff || typeSizeof(i->sType) > 4) {
switch (i->sType) {
case TYPE_F64:
if (reg.data.u64 & 0x00000fffffffffffULL)
return false;
break;
case TYPE_F32:
if (reg.data.u32 & 0xfff)
return false;
} else
if (i->sType == TYPE_S32 || i->sType == TYPE_U32) {
break;
case TYPE_S32:
case TYPE_U32:
// with u32, 0xfffff counts as 0xffffffff as well
if (reg.data.s32 > 0x7ffff || reg.data.s32 < -0x80000)
return false;
break;
case TYPE_U8:
case TYPE_S8:
case TYPE_U16:
case TYPE_S16:
case TYPE_F16:
break;
default:
return false;
}
} else
if (i->op == OP_MAD || i->op == OP_FMA) {