diff --git a/src/amd/vulkan/meta/radv_meta.c b/src/amd/vulkan/meta/radv_meta.c index 463502a92f4..1b1d3e0230c 100644 --- a/src/amd/vulkan/meta/radv_meta.c +++ b/src/amd/vulkan/meta/radv_meta.c @@ -396,7 +396,6 @@ radv_meta_bind_descriptors(struct radv_cmd_buffer *cmd_buffer, VkPipelineBindPoi VK_FROM_HANDLE(radv_pipeline_layout, layout, _layout); struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); struct radv_descriptor_set_layout *set_layout = layout->set[0].layout; - struct radv_cmd_stream *cs = cmd_buffer->cs; uint32_t upload_offset; uint8_t *ptr; @@ -414,24 +413,6 @@ radv_meta_bind_descriptors(struct radv_cmd_buffer *cmd_buffer, VkPipelineBindPoi const uint32_t binding_offset = set_layout->binding[i].offset; radv_GetDescriptorEXT(radv_device_to_handle(device), descriptor, 0, ptr + binding_offset); - - VkImageView image_view = VK_NULL_HANDLE; - if (descriptor->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) { - image_view = descriptor->data.pCombinedImageSampler->imageView; - } else if (descriptor->type == VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE) { - image_view = descriptor->data.pSampledImage->imageView; - } else if (descriptor->type == VK_DESCRIPTOR_TYPE_STORAGE_IMAGE) { - image_view = descriptor->data.pStorageImage->imageView; - } - - /* Buffer descriptors use BDA and they should be added to the list before. */ - if (image_view) { - VK_FROM_HANDLE(radv_image_view, iview, image_view); - for (uint32_t b = 0; b < ARRAY_SIZE(iview->image->bindings); b++) { - if (iview->image->bindings[b].bo) - radv_cs_add_buffer(device->ws, cs->b, iview->image->bindings[b].bo); - } - } } const VkDescriptorBufferBindingInfoEXT descriptor_buffer_binding = { diff --git a/src/amd/vulkan/meta/radv_meta_astc_decode.c b/src/amd/vulkan/meta/radv_meta_astc_decode.c index 4cc867bf63c..4aeed71b26c 100644 --- a/src/amd/vulkan/meta/radv_meta_astc_decode.c +++ b/src/amd/vulkan/meta/radv_meta_astc_decode.c @@ -17,7 +17,6 @@ decode_astc(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *src_ivie struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); struct radv_meta_state *state = &device->meta_state; struct vk_texcompress_astc_write_descriptor_buffer desc_buffer; - struct radv_cmd_stream *cs = cmd_buffer->cs; VkFormat format = src_iview->image->vk.format; int blk_w = vk_format_get_blockwidth(format); int blk_h = vk_format_get_blockheight(format); @@ -26,9 +25,6 @@ decode_astc(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *src_ivie radv_image_view_to_handle(src_iview), layout, radv_image_view_to_handle(dst_iview), format); - VK_FROM_HANDLE(radv_buffer, luts_buf, state->astc_decode->luts_buf); - radv_cs_add_buffer(device->ws, cs->b, luts_buf->bo); - radv_meta_bind_descriptors(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, state->astc_decode->p_layout, VK_TEXCOMPRESS_ASTC_WRITE_DESC_SET_COUNT, desc_buffer.descriptors); diff --git a/src/amd/vulkan/meta/radv_meta_buffer.c b/src/amd/vulkan/meta/radv_meta_buffer.c index a670b6d10b7..c47c267acd5 100644 --- a/src/amd/vulkan/meta/radv_meta_buffer.c +++ b/src/amd/vulkan/meta/radv_meta_buffer.c @@ -287,13 +287,9 @@ uint32_t radv_fill_image(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *image, uint64_t offset, uint64_t size, uint32_t value) { - struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const uint64_t va = image->bindings[0].addr + offset; struct radeon_winsys_bo *bo = image->bindings[0].bo; const enum radv_copy_flags copy_flags = radv_get_copy_flags_from_bo(bo); - struct radv_cmd_stream *cs = cmd_buffer->cs; - - radv_cs_add_buffer(device->ws, cs->b, bo); return radv_fill_memory_internal(cmd_buffer, image, va, size, value, copy_flags); } @@ -302,11 +298,7 @@ uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer, struct radeon_winsys_bo *bo, uint64_t va, uint64_t size, uint32_t value) { - struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const enum radv_copy_flags copy_flags = radv_get_copy_flags_from_bo(bo); - struct radv_cmd_stream *cs = cmd_buffer->cs; - - radv_cs_add_buffer(device->ws, cs->b, bo); return radv_fill_memory(cmd_buffer, va, size, value, copy_flags); } @@ -355,8 +347,6 @@ radv_CmdCopyBuffer2(VkCommandBuffer commandBuffer, const VkCopyBufferInfo2 *pCop VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); VK_FROM_HANDLE(radv_buffer, src_buffer, pCopyBufferInfo->srcBuffer); VK_FROM_HANDLE(radv_buffer, dst_buffer, pCopyBufferInfo->dstBuffer); - struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); - struct radv_cmd_stream *cs = cmd_buffer->cs; const enum radv_copy_flags src_copy_flags = radv_get_copy_flags_from_bo(src_buffer->bo); const enum radv_copy_flags dst_copy_flags = radv_get_copy_flags_from_bo(dst_buffer->bo); @@ -365,9 +355,6 @@ radv_CmdCopyBuffer2(VkCommandBuffer commandBuffer, const VkCopyBufferInfo2 *pCop radv_meta_begin(cmd_buffer); - radv_cs_add_buffer(device->ws, cs->b, src_buffer->bo); - radv_cs_add_buffer(device->ws, cs->b, dst_buffer->bo); - for (unsigned r = 0; r < pCopyBufferInfo->regionCount; r++) { const VkBufferCopy2 *region = &pCopyBufferInfo->pRegions[r]; const uint64_t src_va = vk_buffer_address(&src_buffer->vk, region->srcOffset); @@ -430,9 +417,7 @@ radv_CmdUpdateBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDevice { VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); VK_FROM_HANDLE(radv_buffer, dst_buffer, dstBuffer); - struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const uint64_t dst_va = vk_buffer_address(&dst_buffer->vk, dstOffset); - struct radv_cmd_stream *cs = cmd_buffer->cs; const enum radv_copy_flags dst_copy_flags = radv_get_copy_flags_from_bo(dst_buffer->bo); @@ -440,8 +425,6 @@ radv_CmdUpdateBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDevice radv_meta_begin(cmd_buffer); - radv_cs_add_buffer(device->ws, cs->b, dst_buffer->bo); - radv_update_memory(cmd_buffer, dst_va, dataSize, pData, dst_copy_flags); radv_meta_end(cmd_buffer); diff --git a/src/amd/vulkan/meta/radv_meta_bufimage.c b/src/amd/vulkan/meta/radv_meta_bufimage.c index 831973c97a8..55c0889072b 100644 --- a/src/amd/vulkan/meta/radv_meta_bufimage.c +++ b/src/amd/vulkan/meta/radv_meta_bufimage.c @@ -771,7 +771,6 @@ radv_meta_clear_image_cs_96bit(struct radv_cmd_buffer *cmd_buffer, struct radv_m const VkClearColorValue *clear_color) { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); - struct radv_cmd_stream *cs = cmd_buffer->cs; VkPipelineLayout layout; VkPipeline pipeline; unsigned stride; @@ -783,8 +782,6 @@ radv_meta_clear_image_cs_96bit(struct radv_cmd_buffer *cmd_buffer, struct radv_m return; } - radv_cs_add_buffer(device->ws, cs->b, dst->image->bindings[0].bo); - radv_meta_bind_descriptors(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, layout, 1, (VkDescriptorGetInfoEXT[]){{ .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_GET_INFO_EXT, diff --git a/src/amd/vulkan/meta/radv_meta_clear.c b/src/amd/vulkan/meta/radv_meta_clear.c index 39600205752..6514bc47298 100644 --- a/src/amd/vulkan/meta/radv_meta_clear.c +++ b/src/amd/vulkan/meta/radv_meta_clear.c @@ -600,7 +600,6 @@ clear_htile_mask(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im uint64_t va, uint64_t size, uint32_t htile_value, uint32_t htile_mask) { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); - struct radv_cmd_stream *cs = cmd_buffer->cs; uint64_t block_count = DIV_ROUND_UP(size, 1024); VkPipelineLayout layout; VkPipeline pipeline; @@ -612,8 +611,6 @@ clear_htile_mask(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im return 0; } - radv_cs_add_buffer(device->ws, cs->b, bo); - radv_meta_bind_compute_pipeline(cmd_buffer, pipeline); const unsigned constants[4] = { diff --git a/src/amd/vulkan/meta/radv_meta_copy.c b/src/amd/vulkan/meta/radv_meta_copy.c index 9c0fe5c1df1..3fbd8d005e8 100644 --- a/src/amd/vulkan/meta/radv_meta_copy.c +++ b/src/amd/vulkan/meta/radv_meta_copy.c @@ -304,7 +304,6 @@ radv_CmdCopyBufferToImage2(VkCommandBuffer commandBuffer, const VkCopyBufferToIm VK_FROM_HANDLE(radv_image, dst_image, pCopyBufferToImageInfo->dstImage); struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radv_cmd_stream *cs = cmd_buffer->cs; const enum radv_copy_flags src_copy_flags = radv_get_copy_flags_from_bo(src_buffer->bo); @@ -312,14 +311,8 @@ radv_CmdCopyBufferToImage2(VkCommandBuffer commandBuffer, const VkCopyBufferToIm radv_meta_begin(cmd_buffer); - radv_cs_add_buffer(device->ws, cs->b, src_buffer->bo); - for (unsigned r = 0; r < pCopyBufferToImageInfo->regionCount; r++) { const VkBufferImageCopy2 *region = &pCopyBufferToImageInfo->pRegions[r]; - const VkImageAspectFlags aspect_mask = region->imageSubresource.aspectMask; - const unsigned bind_idx = dst_image->disjoint ? radv_plane_from_aspect(aspect_mask) : 0; - - radv_cs_add_buffer(device->ws, cs->b, dst_image->bindings[bind_idx].bo); if (cmd_buffer->qf == RADV_QUEUE_TRANSFER) { transfer_copy_memory_image(cmd_buffer, src_buffer->vk.device_address, src_buffer->vk.size, src_copy_flags, @@ -451,8 +444,6 @@ radv_CmdCopyImageToBuffer2(VkCommandBuffer commandBuffer, const VkCopyImageToBuf VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); VK_FROM_HANDLE(radv_image, src_image, pCopyImageToBufferInfo->srcImage); VK_FROM_HANDLE(radv_buffer, dst_buffer, pCopyImageToBufferInfo->dstBuffer); - struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); - struct radv_cmd_stream *cs = cmd_buffer->cs; const enum radv_copy_flags dst_copy_flags = radv_get_copy_flags_from_bo(dst_buffer->bo); @@ -460,14 +451,8 @@ radv_CmdCopyImageToBuffer2(VkCommandBuffer commandBuffer, const VkCopyImageToBuf radv_meta_begin(cmd_buffer); - radv_cs_add_buffer(device->ws, cs->b, dst_buffer->bo); - for (unsigned r = 0; r < pCopyImageToBufferInfo->regionCount; r++) { const VkBufferImageCopy2 *region = &pCopyImageToBufferInfo->pRegions[r]; - const VkImageAspectFlags aspect_mask = region->imageSubresource.aspectMask; - const unsigned bind_idx = src_image->disjoint ? radv_plane_from_aspect(aspect_mask) : 0; - - radv_cs_add_buffer(device->ws, cs->b, src_image->bindings[bind_idx].bo); if (cmd_buffer->qf == RADV_QUEUE_TRANSFER) { transfer_copy_memory_image(cmd_buffer, dst_buffer->vk.device_address, dst_buffer->vk.size, dst_copy_flags, @@ -703,7 +688,6 @@ radv_CmdCopyImage2(VkCommandBuffer commandBuffer, const VkCopyImageInfo2 *pCopyI VK_FROM_HANDLE(radv_image, dst_image, pCopyImageInfo->dstImage); struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radv_cmd_stream *cs = cmd_buffer->cs; radv_suspend_conditional_rendering(cmd_buffer); @@ -711,13 +695,6 @@ radv_CmdCopyImage2(VkCommandBuffer commandBuffer, const VkCopyImageInfo2 *pCopyI for (unsigned r = 0; r < pCopyImageInfo->regionCount; r++) { const VkImageCopy2 *region = &pCopyImageInfo->pRegions[r]; - const VkImageAspectFlags src_aspect_mask = region->srcSubresource.aspectMask; - const unsigned src_bind_idx = src_image->disjoint ? radv_plane_from_aspect(src_aspect_mask) : 0; - const VkImageAspectFlags dst_aspect_mask = region->dstSubresource.aspectMask; - const unsigned dst_bind_idx = dst_image->disjoint ? radv_plane_from_aspect(dst_aspect_mask) : 0; - - radv_cs_add_buffer(device->ws, cs->b, src_image->bindings[src_bind_idx].bo); - radv_cs_add_buffer(device->ws, cs->b, dst_image->bindings[dst_bind_idx].bo); if (cmd_buffer->qf == RADV_QUEUE_TRANSFER) { transfer_copy_image(cmd_buffer, src_image, pCopyImageInfo->srcImageLayout, dst_image, diff --git a/src/amd/vulkan/meta/radv_meta_copy_indirect_cs.c b/src/amd/vulkan/meta/radv_meta_copy_indirect_cs.c index 93fc243e570..78b1fb3dc64 100644 --- a/src/amd/vulkan/meta/radv_meta_copy_indirect_cs.c +++ b/src/amd/vulkan/meta/radv_meta_copy_indirect_cs.c @@ -378,7 +378,6 @@ radv_compute_copy_memory_to_image_indirect(struct radv_cmd_buffer *cmd_buffer, const struct radv_physical_device *pdev = radv_device_physical(device); VkImageLayout dst_image_layout = pCopyMemoryToImageIndirectInfo->dstImageLayout; const uint32_t copy_count = pCopyMemoryToImageIndirectInfo->copyCount; - struct radv_cmd_stream *cs = cmd_buffer->cs; uint32_t texel_scale = 1; VkPipelineLayout layout; uint32_t alloc_offset; @@ -409,7 +408,6 @@ radv_compute_copy_memory_to_image_indirect(struct radv_cmd_buffer *cmd_buffer, for (uint32_t i = 0; i < copy_count; i++) { const VkImageSubresourceLayers *imageSubresource = &pCopyMemoryToImageIndirectInfo->pImageSubresources[i]; const VkImageAspectFlags aspect_mask = imageSubresource->aspectMask; - const unsigned bind_idx = dst_image->disjoint ? radv_plane_from_aspect(aspect_mask) : 0; struct radv_image_view dst_iview; /* The Vulkan spec 1.4.343 says: @@ -435,8 +433,6 @@ radv_compute_copy_memory_to_image_indirect(struct radv_cmd_buffer *cmd_buffer, radv_meta_bind_compute_pipeline(cmd_buffer, pipeline); - radv_cs_add_buffer(device->ws, cs->b, dst_image->bindings[bind_idx].bo); - struct radv_meta_blit2d_surf img_bsurf = radv_blit_surf_for_image_level_layer( dst_image, pCopyMemoryToImageIndirectInfo->dstImageLayout, imageSubresource); diff --git a/src/amd/vulkan/meta/radv_meta_copy_indirect_fs.c b/src/amd/vulkan/meta/radv_meta_copy_indirect_fs.c index 6fc9572cb14..0d45eaf89ff 100644 --- a/src/amd/vulkan/meta/radv_meta_copy_indirect_fs.c +++ b/src/amd/vulkan/meta/radv_meta_copy_indirect_fs.c @@ -213,13 +213,10 @@ radv_gfx_copy_memory_to_image_indirect(struct radv_cmd_buffer *cmd_buffer, const struct radv_physical_device *pdev = radv_device_physical(device); VkImageLayout dst_image_layout = pCopyMemoryToImageIndirectInfo->dstImageLayout; const uint32_t copy_count = pCopyMemoryToImageIndirectInfo->copyCount; - struct radv_cmd_stream *cs = cmd_buffer->cs; VkResult result; for (uint32_t i = 0; i < copy_count; i++) { const VkImageSubresourceLayers *imageSubresource = &pCopyMemoryToImageIndirectInfo->pImageSubresources[i]; - const VkImageAspectFlags aspect_mask = imageSubresource->aspectMask; - const unsigned bind_idx = dst_image->disjoint ? radv_plane_from_aspect(aspect_mask) : 0; struct radv_image_view dst_iview; VkPipelineLayout layout; VkPipeline pipeline; @@ -228,8 +225,6 @@ radv_gfx_copy_memory_to_image_indirect(struct radv_cmd_buffer *cmd_buffer, const VkExtent3D img_extent_el = vk_image_extent_to_elements(&dst_image->vk, (VkExtent3D){extent.width, extent.height, extent.depth}); - radv_cs_add_buffer(device->ws, cs->b, dst_image->bindings[bind_idx].bo); - struct radv_meta_blit2d_surf img_bsurf = radv_blit_surf_for_image_level_layer( dst_image, pCopyMemoryToImageIndirectInfo->dstImageLayout, imageSubresource); diff --git a/src/amd/vulkan/meta/radv_meta_dcc_retile.c b/src/amd/vulkan/meta/radv_meta_dcc_retile.c index 43a421a8c3d..bd0e71298d3 100644 --- a/src/amd/vulkan/meta/radv_meta_dcc_retile.c +++ b/src/amd/vulkan/meta/radv_meta_dcc_retile.c @@ -111,7 +111,6 @@ void radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image) { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); - struct radv_cmd_stream *cs = cmd_buffer->cs; VkPipelineLayout layout; VkPipeline pipeline; VkResult result; @@ -135,8 +134,6 @@ radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image) const uint64_t va = image->bindings[0].addr; - radv_cs_add_buffer(device->ws, cs->b, image->bindings[0].bo); - radv_meta_bind_descriptors(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, layout, 2, (VkDescriptorGetInfoEXT[]){ { diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index ad316933949..d690fe815ec 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -5488,8 +5488,6 @@ radv_gfx11_emit_vrs_surface(struct radv_cmd_buffer *cmd_buffer) const struct radv_image *vrs_image = vrs_iview->image; - radv_cs_add_buffer(device->ws, cs->b, vrs_image->bindings[0].bo); - const uint64_t va = vrs_image->bindings[0].addr | (vrs_image->planes[0].surface.tile_swizzle << 8); const uint32_t xmax = vrs_iview->vk.extent.width - 1; const uint32_t ymax = vrs_iview->vk.extent.height - 1; @@ -5551,20 +5549,9 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) VkImageLayout layout = render->color_att[i].layout; - radv_cs_add_buffer(device->ws, cs->b, iview->image->bindings[0].bo); - assert(iview->vk.aspects & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT | VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT)); - if (iview->image->disjoint && iview->vk.aspects == VK_IMAGE_ASPECT_COLOR_BIT) { - for (uint32_t plane_id = 0; plane_id < iview->image->plane_count; plane_id++) { - radv_cs_add_buffer(device->ws, cs->b, iview->image->bindings[plane_id].bo); - } - } else { - uint32_t plane_id = iview->image->disjoint ? iview->plane_id : 0; - radv_cs_add_buffer(device->ws, cs->b, iview->image->bindings[plane_id].bo); - } - if (pdev->info.gfx_level >= GFX12) { radv_gfx12_emit_fb_color_state(cmd_buffer, i, &render->color_att[i].cb); } else if (pdev->info.gfx_level >= GFX11) { @@ -5608,8 +5595,6 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) struct radv_image_view *iview = render->ds_att.iview; const struct radv_image *image = iview->image; - radv_cs_add_buffer(device->ws, cs->b, image->bindings[0].bo); - uint32_t qf_mask = radv_image_queue_family_mask(image, cmd_buffer->qf, cmd_buffer->qf); if (render->ds_att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) { @@ -7907,10 +7892,8 @@ radv_CmdBindVertexBuffers2(VkCommandBuffer commandBuffer, uint32_t firstBinding, const VkDeviceSize *pStrides) { VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); - struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings; struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; - struct radv_cmd_stream *cs = cmd_buffer->cs; /* We have to defer setting up vertex buffer since we need the buffer * stride from the pipeline. */ @@ -7939,7 +7922,6 @@ radv_CmdBindVertexBuffers2(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bit = BITFIELD_BIT(idx); if (buffer) { - radv_cs_add_buffer(device->ws, cs->b, buffer->bo); cmd_buffer->state.vbo_bound_mask |= bit; } else { cmd_buffer->state.vbo_bound_mask &= ~bit; @@ -7993,8 +7975,6 @@ radv_CmdBindIndexBuffer2(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDevic { VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); VK_FROM_HANDLE(radv_buffer, index_buffer, buffer); - struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); - struct radv_cmd_stream *cs = cmd_buffer->cs; cmd_buffer->state.index_type = vk_to_index_type(indexType); @@ -8003,7 +7983,6 @@ radv_CmdBindIndexBuffer2(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDevic int index_size = radv_get_vgt_index_size(vk_to_index_type(indexType)); cmd_buffer->state.max_index_count = (vk_buffer_range(&index_buffer->vk, offset, size)) / index_size; - radv_cs_add_buffer(device->ws, cs->b, index_buffer->bo); } else { cmd_buffer->state.index_va = 0; cmd_buffer->state.max_index_count = 0; @@ -13218,8 +13197,6 @@ radv_CmdDrawIndirect(VkCommandBuffer commandBuffer, VkBuffer _buffer, VkDeviceSi { VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); VK_FROM_HANDLE(radv_buffer, buffer, _buffer); - struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); - struct radv_cmd_stream *cs = cmd_buffer->cs; struct radv_draw_info info; info.count = drawCount; @@ -13230,8 +13207,6 @@ radv_CmdDrawIndirect(VkCommandBuffer commandBuffer, VkBuffer _buffer, VkDeviceSi info.indexed = false; info.instance_count = 0; - radv_cs_add_buffer(device->ws, cs->b, buffer->bo); - if (!radv_before_draw(cmd_buffer, &info, 1, false)) return; radv_emit_indirect_draw_packets(cmd_buffer, &info); @@ -13244,8 +13219,6 @@ radv_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer, VkBuffer _buffer, VkD { VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); VK_FROM_HANDLE(radv_buffer, buffer, _buffer); - struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); - struct radv_cmd_stream *cs = cmd_buffer->cs; struct radv_draw_info info; info.indexed = true; @@ -13256,8 +13229,6 @@ radv_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer, VkBuffer _buffer, VkD info.strmout_va = 0; info.instance_count = 0; - radv_cs_add_buffer(device->ws, cs->b, buffer->bo); - if (!radv_before_draw(cmd_buffer, &info, 1, false)) return; radv_emit_indirect_draw_packets(cmd_buffer, &info); @@ -13271,8 +13242,6 @@ radv_CmdDrawIndirectCount(VkCommandBuffer commandBuffer, VkBuffer _buffer, VkDev VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); VK_FROM_HANDLE(radv_buffer, buffer, _buffer); VK_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer); - struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); - struct radv_cmd_stream *cs = cmd_buffer->cs; struct radv_draw_info info; info.count = maxDrawCount; @@ -13283,9 +13252,6 @@ radv_CmdDrawIndirectCount(VkCommandBuffer commandBuffer, VkBuffer _buffer, VkDev info.indexed = false; info.instance_count = 0; - radv_cs_add_buffer(device->ws, cs->b, buffer->bo); - radv_cs_add_buffer(device->ws, cs->b, count_buffer->bo); - if (!radv_before_draw(cmd_buffer, &info, 1, false)) return; radv_emit_indirect_draw_packets(cmd_buffer, &info); @@ -13300,8 +13266,6 @@ radv_CmdDrawIndexedIndirectCount(VkCommandBuffer commandBuffer, VkBuffer _buffer VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); VK_FROM_HANDLE(radv_buffer, buffer, _buffer); VK_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer); - struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); - struct radv_cmd_stream *cs = cmd_buffer->cs; struct radv_draw_info info; info.indexed = true; @@ -13312,9 +13276,6 @@ radv_CmdDrawIndexedIndirectCount(VkCommandBuffer commandBuffer, VkBuffer _buffer info.strmout_va = 0; info.instance_count = 0; - radv_cs_add_buffer(device->ws, cs->b, buffer->bo); - radv_cs_add_buffer(device->ws, cs->b, count_buffer->bo); - if (!radv_before_draw(cmd_buffer, &info, 1, false)) return; radv_emit_indirect_draw_packets(cmd_buffer, &info); @@ -13368,8 +13329,6 @@ radv_CmdDrawMeshTasksIndirectEXT(VkCommandBuffer commandBuffer, VkBuffer _buffer info.indexed = false; info.instance_count = 0; - radv_cs_add_buffer(device->ws, cs->b, buffer->bo); - if (!radv_before_taskmesh_draw(cmd_buffer, &info, drawCount, false)) return; @@ -13404,9 +13363,6 @@ radv_CmdDrawMeshTasksIndirectCountEXT(VkCommandBuffer commandBuffer, VkBuffer _b info.indexed = false; info.instance_count = 0; - radv_cs_add_buffer(device->ws, cs->b, buffer->bo); - radv_cs_add_buffer(device->ws, cs->b, count_buffer->bo); - if (!radv_before_taskmesh_draw(cmd_buffer, &info, maxDrawCount, false)) return; @@ -14074,11 +14030,7 @@ radv_CmdDispatchIndirect(VkCommandBuffer commandBuffer, VkBuffer _buffer, VkDevi { VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); VK_FROM_HANDLE(radv_buffer, buffer, _buffer); - struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); struct radv_dispatch_info info = {.indirect_va = vk_buffer_address(&buffer->vk, offset)}; - struct radv_cmd_stream *cs = cmd_buffer->cs; - - radv_cs_add_buffer(device->ws, cs->b, buffer->bo); radv_compute_dispatch(cmd_buffer, &info); } @@ -15220,15 +15172,11 @@ radv_CmdBeginConditionalRenderingEXT(VkCommandBuffer commandBuffer, { VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); VK_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer); - struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); - struct radv_cmd_stream *cs = cmd_buffer->cs; bool draw_visible = true; uint64_t va; va = vk_buffer_address(&buffer->vk, pConditionalRenderingBegin->offset); - radv_cs_add_buffer(device->ws, cs->b, buffer->bo); - /* By default, if the 32-bit value at offset in buffer memory is zero, * then the rendering commands are discarded, otherwise they are * executed as normal. If the inverted flag is set, all commands are @@ -15256,9 +15204,7 @@ radv_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer, uint32_t const VkDeviceSize *pSizes) { VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); - struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings; - struct radv_cmd_stream *cs = cmd_buffer->cs; uint8_t enabled_mask = 0; assert(firstBinding + bindingCount <= MAX_SO_BUFFERS); @@ -15274,8 +15220,6 @@ radv_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer, uint32_t sb[idx].size = pSizes[i]; } - radv_cs_add_buffer(device->ws, cs->b, buffer->bo); - enabled_mask |= 1 << idx; } @@ -15413,8 +15357,6 @@ radv_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstC counter_buffer_offset = pCounterBufferOffsets[counter_buffer_idx]; va += vk_buffer_address(&buffer->vk, counter_buffer_offset); - - radv_cs_add_buffer(device->ws, cs->b, buffer->bo); } if (pdev->info.gfx_level >= GFX12) { @@ -15520,8 +15462,6 @@ radv_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCou va += vk_buffer_address(&buffer->vk, counter_buffer_offset); - radv_cs_add_buffer(device->ws, cs->b, buffer->bo); - needs_pfp_sync_me = true; } @@ -15630,8 +15570,6 @@ radv_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer, uint32_t instanc info.indexed = false; info.indirect_va = 0; - radv_cs_add_buffer(device->ws, cs->b, counterBuffer->bo); - if (!radv_before_draw(cmd_buffer, &info, 1, false)) return; struct VkMultiDrawInfoEXT minfo = {0, 0}; @@ -15662,8 +15600,6 @@ radv_CmdWriteBufferMarker2AMD(VkCommandBuffer commandBuffer, VkPipelineStageFlag struct radv_cmd_stream *cs = cmd_buffer->cs; const uint64_t va = vk_buffer_address(&buffer->vk, dstOffset); - radv_cs_add_buffer(device->ws, cs->b, buffer->bo); - if (cmd_buffer->qf == RADV_QUEUE_TRANSFER) { radeon_check_space(device->ws, cs->b, 4); ac_emit_sdma_fence(cmd_buffer->cs->b, va, marker); diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index e26a8bd0762..0c3cdba541d 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -2467,7 +2467,6 @@ radv_CmdCopyQueryPoolResults(VkCommandBuffer commandBuffer, VkQueryPool queryPoo radv_suspend_conditional_rendering(cmd_buffer); radv_cs_add_buffer(device->ws, cs->b, pool->bo); - radv_cs_add_buffer(device->ws, cs->b, dst_buffer->bo); /* Workaround engines that forget to properly specify WAIT_BIT because some driver implicitly * synchronizes before query copy. @@ -2522,6 +2521,7 @@ radv_CmdResetQueryPool(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uin VK_FROM_HANDLE(radv_query_pool, pool, queryPool); struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); + struct radv_cmd_stream *cs = cmd_buffer->cs; uint32_t value = query_clear_value(pool->vk.query_type); uint32_t flush_bits = 0; @@ -2537,6 +2537,8 @@ radv_CmdResetQueryPool(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uin radv_meta_begin(cmd_buffer); + radv_cs_add_buffer(device->ws, cs->b, pool->bo); + flush_bits |= radv_fill_buffer(cmd_buffer, pool->bo, radv_buffer_get_va(pool->bo) + firstQuery * pool->stride, queryCount * pool->stride, value); diff --git a/src/amd/vulkan/radv_video.c b/src/amd/vulkan/radv_video.c index 7f9df736f4b..360635d6668 100644 --- a/src/amd/vulkan/radv_video.c +++ b/src/amd/vulkan/radv_video.c @@ -1383,7 +1383,6 @@ radv_CmdControlVideoCodingKHR(VkCommandBuffer commandBuffer, const VkVideoCoding if (vid->sessionctx.mem) { cmd.session_va = radv_buffer_get_va(vid->sessionctx.mem->bo) + vid->sessionctx.offset; - radv_cs_add_buffer(device->ws, cs->b, vid->sessionctx.mem->bo); } if (vid->dec->embedded_size) { @@ -2066,8 +2065,6 @@ fill_surface(struct radv_cmd_buffer *cmd_buf, struct radv_image *img, uint32_t s surf->planes[i].surf = &img->planes[i].surface; } } - - radv_cs_add_buffer(radv_cmd_buffer_device(cmd_buf)->ws, cmd_buf->cs->b, img->bindings[0].bo); } static enum ac_video_dec_tier @@ -2117,7 +2114,6 @@ radv_CmdDecodeVideoKHR(VkCommandBuffer commandBuffer, const VkVideoDecodeInfoKHR if (vid->sessionctx.mem) { cmd.session_va = radv_buffer_get_va(vid->sessionctx.mem->bo) + vid->sessionctx.offset; - radv_cs_add_buffer(device->ws, cs->b, vid->sessionctx.mem->bo); } if (vid->dec->embedded_size) { @@ -2144,7 +2140,6 @@ radv_CmdDecodeVideoKHR(VkCommandBuffer commandBuffer, const VkVideoDecodeInfoKHR } cmd.bitstream_va += vk_buffer_address(&src_buffer->vk, frame_info->srcBufferOffset); - radv_cs_add_buffer(device->ws, cs->b, src_buffer->bo); VK_FROM_HANDLE(radv_image_view, db, frame_info->dstPictureResource.imageViewBinding); uint32_t db_slice = db->vk.base_array_layer + frame_info->dstPictureResource.baseArrayLayer; diff --git a/src/amd/vulkan/radv_video_enc.c b/src/amd/vulkan/radv_video_enc.c index b7485a68c1b..9664162352e 100644 --- a/src/amd/vulkan/radv_video_enc.c +++ b/src/amd/vulkan/radv_video_enc.c @@ -425,9 +425,6 @@ radv_enc_session_info(struct radv_cmd_buffer *cmd_buffer) { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radv_cmd_stream *cs = cmd_buffer->cs; - - radv_cs_add_buffer(device->ws, cs->b, cmd_buffer->video.vid->sessionctx.mem->bo); uint64_t va = radv_buffer_get_va(cmd_buffer->video.vid->sessionctx.mem->bo); va += cmd_buffer->video.vid->sessionctx.offset; @@ -1587,7 +1584,6 @@ radv_enc_ctx(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *inf struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); struct radv_video_session *vid = cmd_buffer->video.vid; - struct radv_cmd_stream *cs = cmd_buffer->cs; struct radv_image_view *dpb_iv = NULL; struct radv_image *dpb = NULL; uint64_t va = 0; @@ -1614,7 +1610,6 @@ radv_enc_ctx(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *inf uint32_t luma_size = 0, chroma_size = 0, colloc_bytes = 0; dpb_image_sizes(dpb, &luma_pitch, &luma_size, &chroma_size, &colloc_bytes); - radv_cs_add_buffer(device->ws, cs->b, dpb->bindings[0].bo); va = dpb->bindings[0].addr; uint32_t swizzle_mode = 0; @@ -1733,7 +1728,6 @@ radv_enc_ctx2(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *in uint32_t luma_pitch = 0, luma_size = 0, chroma_size = 0, colloc_bytes = 0; int max_ref_slot_idx = 0; const VkVideoPictureResourceInfoKHR *slots[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES] = {NULL}; - struct radv_cmd_stream *cs = cmd_buffer->cs; bool intra_only_dpb = false; if (info->pSetupReferenceSlot) { @@ -1773,7 +1767,6 @@ radv_enc_ctx2(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *in struct radv_image_view *dpb_iv = radv_image_view_from_handle(res->imageViewBinding); assert(dpb_iv != NULL); struct radv_image *dpb_img = intra_only_dpb ? vid->intra_only_dpb : dpb_iv->image; - radv_cs_add_buffer(device->ws, cs->b, dpb_img->bindings[0].bo); dpb_image_sizes(dpb_img, &luma_pitch, &luma_size, &chroma_size, &colloc_bytes); uint32_t metadata_size = RENCODE_MAX_METADATA_BUFFER_SIZE_PER_FRAME; @@ -1826,9 +1819,7 @@ radv_enc_bitstream(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buffe { struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radv_cmd_stream *cs = cmd_buffer->cs; uint64_t va = vk_buffer_address(&buffer->vk, offset); - radv_cs_add_buffer(device->ws, cs->b, buffer->bo); RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.bitstream); RADEON_ENC_CS(RENCODE_REC_SWIZZLE_MODE_LINEAR); @@ -1914,7 +1905,6 @@ radv_enc_intra_refresh(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeIn static void radv_enc_qp_map_input(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoEncodeInfoKHR *enc_info) { - struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct VkVideoEncodeQuantizationMapInfoKHR *quantization_map_info = vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_QUANTIZATION_MAP_INFO_KHR); const struct radv_image_view *qp_map_view = @@ -1926,11 +1916,9 @@ radv_enc_qp_map_input(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoEn return; const uint64_t va_in = qp_map->bindings[0].addr; - radv_cs_add_buffer(device->ws, cs->b, qp_map->bindings[0].bo); const uint64_t va_out = radv_buffer_get_va(cmd_buffer->video.vid->qp_map.mem->bo) + cmd_buffer->video.vid->qp_map.offset; - radv_cs_add_buffer(device->ws, cmd_buffer->cs->b, cmd_buffer->video.vid->qp_map.mem->bo); radv_vcn_sq_header(cs, &cmd_buffer->video.sq, RADEON_VCN_ENGINE_TYPE_COMMON); @@ -1981,7 +1969,6 @@ radv_enc_qp_map(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoEncodeIn uint32_t rc_method = radv_enc_rate_control_method(cmd_buffer->video.enc.rate_control_mode); const uint32_t qp_map_type = rc_method == RENCODE_RATE_CONTROL_METHOD_NONE ? RENCODE_QP_MAP_TYPE_DELTA : RENCODE_QP_MAP_TYPE_MAP_PA; - radv_cs_add_buffer(device->ws, cmd_buffer->cs->b, qp_map->bindings[0].bo); const uint64_t va = qp_map->bindings[0].addr; RADEON_ENC_CS(qp_map_type); RADEON_ENC_CS(va >> 32); @@ -2074,7 +2061,6 @@ radv_enc_params(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR * struct radv_image *src_img = src_iv->image; struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radv_cmd_stream *cs = cmd_buffer->cs; uint32_t array_idx = enc_info->srcPictureResource.baseArrayLayer + src_iv->vk.base_array_layer; uint64_t va = src_img->bindings[0].addr; uint64_t luma_va = va + src_img->planes[0].surface.u.gfx9.surf_offset + @@ -2086,7 +2072,6 @@ radv_enc_params(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR * unsigned int slot_idx = 0xffffffff; unsigned int max_layers = cmd_buffer->video.enc.rate_control_num_layers; - radv_cs_add_buffer(device->ws, cs->b, src_img->bindings[0].bo); if (h264_pic) { switch (h264_pic->primary_pic_type) { case STD_VIDEO_H264_PICTURE_TYPE_P: @@ -2558,14 +2543,12 @@ radv_enc_headers_hevc(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInf static void radv_enc_cdf_default_table(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info) { - struct radv_cmd_stream *cs = cmd_buffer->cs; struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); const struct radv_physical_device *pdev = radv_device_physical(device); const struct VkVideoEncodeAV1PictureInfoKHR *av1_picture_info = vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_AV1_PICTURE_INFO_KHR); const StdVideoEncodeAV1PictureInfo *av1_pic = av1_picture_info->pStdPictureInfo; - radv_cs_add_buffer(device->ws, cs->b, cmd_buffer->video.vid->default_cdf.mem->bo); uint64_t va = radv_buffer_get_va(cmd_buffer->video.vid->default_cdf.mem->bo); va += cmd_buffer->video.vid->default_cdf.offset; uint32_t use_cdf_default = (av1_pic->frame_type == STD_VIDEO_AV1_FRAME_TYPE_KEY ||