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panvk: Fix valhall_pack_buf_idx()
The descriptor lowering pass can add UBO loads to read descriptors, and
these loads already assume a nir_address_format_32bit_index_offset
format.
Bail out if we detect that case in valhall_pack_buf_idx().
Reported-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: 27beadcbdb ("panvk: Extend the shader logic to support Valhall")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Rebecca Mckeever <rebecca.mckeever@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: John Anthony <john.anthony@arm.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30969>
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1 changed files with 7 additions and 1 deletions
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@ -387,9 +387,15 @@ valhall_pack_buf_idx(nir_builder *b, nir_instr *instr, UNUSED void *data)
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intrin->intrinsic != nir_intrinsic_load_ssbo)
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return false;
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b->cursor = nir_before_instr(&intrin->instr);
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nir_def *index = intrin->src[0].ssa;
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/* The descriptor lowering pass can add UBO loads, and those already have the
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* right index format. */
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if (index->num_components == 1)
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return false;
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b->cursor = nir_before_instr(&intrin->instr);
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/* The valhall backend expects nir_address_format_32bit_index_offset,
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* but address mode is nir_address_format_vec2_index_32bit_offset to allow
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* us to store the array size, set and index without losing information
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