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ac/surface: rename gfx9_dcc_equation to gfx9_meta_equation

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gfx9_meta_equation will be used to store the HTILE equation.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10187>
This commit is contained in:
Samuel Pitoiset 2021-04-13 13:32:44 +02:00 • committed by Marge Bot
parent 1edda9e878
commit 9eee737364
3 changed files with 15 additions and 11 deletions
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6
src/amd/common/ac_surface.c
View file

@ -1495,14 +1495,14 @@ static bool is_dcc_supported_by_DCN(const struct radeon_info *info,
static void ac_copy_dcc_equation(const struct radeon_info *info,
ADDR2_COMPUTE_DCCINFO_OUTPUT *dcc,
struct gfx9_dcc_equation *equation)
struct gfx9_meta_equation *equation)
{
equation->meta_block_width = dcc->metaBlkWidth;
equation->meta_block_height = dcc->metaBlkHeight;
equation->meta_block_depth = dcc->metaBlkDepth;
if (info->chip_class >= GFX10) {
/* gfx9_dcc_equation doesn't store the first 4 and the last 8 elements. They must be 0. */
/* gfx9_meta_equation doesn't store the first 4 and the last 8 elements. They must be 0. */
for (unsigned i = 0; i < 4; i++)
assert(dcc->equation.gfx10_bits[i] == 0);
@ -2893,7 +2893,7 @@ void ac_surface_print_info(FILE *out, const struct radeon_info *info,
}
nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info *info,
unsigned bpe, struct gfx9_dcc_equation *equation,
unsigned bpe, struct gfx9_meta_equation *equation,
nir_ssa_def *dcc_pitch, nir_ssa_def *dcc_height,
nir_ssa_def *dcc_slice_size,
nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z,

12
src/amd/common/ac_surface.h
View file

@ -171,6 +171,10 @@ struct gfx9_surf_level {
};
/**
* Meta address equation.
*
* For DCC:
*
* DCC address equation for doing DCC address computations in shaders.
*
* ac_surface_dcc_address_test.c contains the reference implementation.
@ -180,7 +184,7 @@ struct gfx9_surf_level {
* The gfx10 equation doesn't support mipmapping and MSAA.
* (those are also limitations of Addr2ComputeDccAddrFromCoord)
*/
struct gfx9_dcc_equation {
struct gfx9_meta_equation {
uint16_t meta_block_width;
uint16_t meta_block_height;
uint16_t meta_block_depth;
@ -272,8 +276,8 @@ struct gfx9_surf_layout {
struct gfx9_surf_level cmask_level0;
/* For DCC retiling. */
struct gfx9_dcc_equation dcc_equation; /* 2D only */
struct gfx9_dcc_equation display_dcc_equation;
struct gfx9_meta_equation dcc_equation; /* 2D only */
struct gfx9_meta_equation display_dcc_equation;
} color;
/* Z/S */
@ -449,7 +453,7 @@ void ac_surface_print_info(FILE *out, const struct radeon_info *info,
#ifdef AC_SURFACE_INCLUDE_NIR
nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info *info,
unsigned bpe, struct gfx9_dcc_equation *equation,
unsigned bpe, struct gfx9_meta_equation *equation,
nir_ssa_def *dcc_pitch, nir_ssa_def *dcc_height,
nir_ssa_def *dcc_slice_size,
nir_ssa_def *x, nir_ssa_def *y, nir_ssa_def *z,

8
src/amd/common/ac_surface_meta_address_test.c
View file

@ -247,13 +247,13 @@ static bool one_dcc_address_test(const char *name, const char *test, ADDR_HANDLE
in.height = dout.height;
in.pipeXor = xout.pipeBankXor;
/* Validate that the packed gfx9_dcc_equation structure can fit all fields. */
const struct gfx9_dcc_equation eq;
/* Validate that the packed gfx9_meta_equation structure can fit all fields. */
const struct gfx9_meta_equation eq;
if (info->chip_class == GFX9) {
/* The bit array is smaller in gfx9_dcc_equation than in addrlib. */
/* The bit array is smaller in gfx9_meta_equation than in addrlib. */
assert(dout.equation.gfx9.num_bits <= ARRAY_SIZE(eq.u.gfx9.bit));
} else {
/* gfx9_dcc_equation doesn't store the first 4 and the last 8 elements. They must be 0. */
/* gfx9_meta_equation doesn't store the first 4 and the last 8 elements. They must be 0. */
for (unsigned i = 0; i < 4; i++)
assert(dout.equation.gfx10_bits[i] == 0);