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aco/isel: emit v_mul_f64 with modifiers for fneg/fabs

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Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38011>
This commit is contained in:
Georg Lehmann 2025-10-22 18:37:41 +02:00 • committed by Marge Bot
parent c84f60ef08
commit 9ece74ce79
1 changed files with 5 additions and 14 deletions
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19
src/amd/compiler/instruction_selection/aco_select_nir_alu.cpp
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@ -2099,13 +2099,8 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand::c32(0xbf800000u),
as_vgpr(ctx, src));
} else if (dst.regClass() == v2) {
if (ctx->block->fp_mode.must_flush_denorms16_64)
src = bld.vop3(aco_opcode::v_mul_f64_e64, bld.def(v2), Operand::c64(0x3FF0000000000000),
as_vgpr(ctx, src));
Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), Operand::c32(0x80000000u), upper);
bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
bld.vop3(aco_opcode::v_mul_f64_e64, Definition(dst), Operand::c64(0xBFF0000000000000),
as_vgpr(ctx, src));
} else if (dst.regClass() == s1 && instr->def.bit_size == 16) {
bld.sop2(aco_opcode::s_mul_f16, Definition(dst), Operand::c16(0xbc00u), src);
} else if (dst.regClass() == s1 && instr->def.bit_size == 32) {
@ -2139,13 +2134,9 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
.instr;
mul->valu().abs[1] = true;
} else if (dst.regClass() == v2) {
if (ctx->block->fp_mode.must_flush_denorms16_64)
src = bld.vop3(aco_opcode::v_mul_f64_e64, bld.def(v2), Operand::c64(0x3FF0000000000000),
as_vgpr(ctx, src));
Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
upper = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand::c32(0x7FFFFFFFu), upper);
bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
Instruction* mul = bld.vop3(aco_opcode::v_mul_f64_e64, Definition(dst),
Operand::c64(0x3FF0000000000000), as_vgpr(ctx, src));
mul->valu().abs[1] = true;
} else if (dst.regClass() == s1 && instr->def.bit_size == 16) {
Temp mask = bld.copy(bld.def(s1), Operand::c32(0x7fff));
if (ctx->block->fp_mode.denorm16_64 == fp_denorm_keep) {