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i965/gen6: Fix scissors using invalid STATE_BASE_ADDRESS.

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The scissor state was incorrectly in a .prepare function instead of
.emit, so the packet would end up in the batch before the
STATE_BASE_ADDRESS.  It appears that this doesn't actually hurt, as
the scissor address gets dereferenced according to the current SBA at
draw time.
(cherry picked from commit cd7bfd5d44)
This commit is contained in:
Eric Anholt 2011-06-19 11:33:40 -07:00
parent 8d9202c162
commit 9eace71048
1 changed files with 2 additions and 2 deletions
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4
src/mesa/drivers/dri/i965/gen6_scissor_state.c
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@ -31,7 +31,7 @@
#include "intel_batchbuffer.h"
static void
gen6_prepare_scissor_state(struct brw_context *brw)
gen6_upload_scissor_state(struct brw_context *brw)
{
struct intel_context *intel = &brw->intel;
struct gl_context *ctx = &intel->ctx;
@ -89,5 +89,5 @@ const struct brw_tracked_state gen6_scissor_state = {
.brw = BRW_NEW_BATCH,
.cache = 0,
},
.prepare = gen6_prepare_scissor_state,
.emit = gen6_upload_scissor_state,
};