From 9e5cd02faec4a272da24ff7ea8e8d1f6b6c3f44e Mon Sep 17 00:00:00 2001 From: Erik Faye-Lund Date: Mon, 5 Jun 2023 12:41:14 +0200 Subject: [PATCH] nir: isub -> iadd_imm Reviewed-by: Faith Ekstrand Part-of: --- src/amd/common/ac_nir_lower_ngg.c | 4 ++-- src/compiler/nir/nir_lower_fp16_conv.c | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/amd/common/ac_nir_lower_ngg.c b/src/amd/common/ac_nir_lower_ngg.c index 9ce9f7bf3bf..93648abae71 100644 --- a/src/amd/common/ac_nir_lower_ngg.c +++ b/src/amd/common/ac_nir_lower_ngg.c @@ -2910,9 +2910,9 @@ ngg_gs_export_primitives(nir_builder *b, nir_ssa_def *max_num_out_prims, nir_ssa nir_ssa_def *vtx_indices[3] = {0}; vtx_indices[s->num_vertices_per_primitive - 1] = exporter_tid_in_tg; if (s->num_vertices_per_primitive >= 2) - vtx_indices[s->num_vertices_per_primitive - 2] = nir_isub(b, exporter_tid_in_tg, nir_imm_int(b, 1)); + vtx_indices[s->num_vertices_per_primitive - 2] = nir_iadd_imm(b, exporter_tid_in_tg, -1); if (s->num_vertices_per_primitive == 3) - vtx_indices[s->num_vertices_per_primitive - 3] = nir_isub(b, exporter_tid_in_tg, nir_imm_int(b, 2)); + vtx_indices[s->num_vertices_per_primitive - 3] = nir_iadd_imm(b, exporter_tid_in_tg, -2); if (s->num_vertices_per_primitive == 3) { /* API GS outputs triangle strips, but NGG HW understands triangles. diff --git a/src/compiler/nir/nir_lower_fp16_conv.c b/src/compiler/nir/nir_lower_fp16_conv.c index ea6500c89a9..b88406a6e2f 100644 --- a/src/compiler/nir/nir_lower_fp16_conv.c +++ b/src/compiler/nir/nir_lower_fp16_conv.c @@ -113,9 +113,9 @@ float_to_half_impl(nir_builder *b, nir_ssa_def *src, nir_rounding_mode mode) /* FP16 will be normal */ nir_ssa_def *value = nir_ior(b, nir_ishl_imm(b, - nir_isub(b, - nir_ushr_imm(b, abs, 23), - nir_imm_int(b, 112)), + nir_iadd_imm(b, + nir_ushr_imm(b, abs, 23), + -112), 10), nir_iand_imm(b, nir_ushr_imm(b, abs, 13), 0x3FFF)); nir_ssa_def *guard = nir_iand(b, nir_ushr_imm(b, abs, 12), one);