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treewide: use nir_load_global alias of nir_build_load_global

Browse source 
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37959>
This commit is contained in:
Georg Lehmann 2025-10-20 16:51:09 +02:00
parent 77540cac8c
commit 9e41a7c139
21 changed files with 153 additions and 158 deletions
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2
src/amd/common/nir/ac_nir.c
View file

@ -328,7 +328,7 @@ ac_nir_load_smem(nir_builder *b, unsigned num_components, nir_def *addr, nir_def
else
addr = nir_iadd(b, addr, nir_u2u64(b, offset));
return nir_build_load_global(b, num_components, 32, addr,
return nir_load_global(b, num_components, 32, addr,
.align_mul = align_mul,
.access = access | ACCESS_CAN_REORDER | ACCESS_NON_WRITEABLE | ACCESS_SMEM_AMD);
}

6
src/amd/vulkan/nir/radv_meta_nir.c
View file

@ -168,7 +168,7 @@ radv_meta_nir_build_copy_memory_shader(struct radv_device *dev, uint32_t bytes_p
nir_def *offset = nir_u2u64(&b, nir_umin(&b, nir_imul_imm(&b, global_id, bytes_per_invocation), max_offset));
nir_def *data =
nir_build_load_global(&b, num_components, bit_size, nir_iadd(&b, src_addr, offset), .align_mul = bit_size / 8);
nir_load_global(&b, num_components, bit_size, nir_iadd(&b, src_addr, offset), .align_mul = bit_size / 8);
nir_build_store_global(&b, data, nir_iadd(&b, dst_addr, offset), .align_mul = bit_size / 8);
return b.shader;
@ -886,7 +886,7 @@ radv_meta_nir_build_clear_htile_mask_shader(struct radv_device *dev)
nir_def *va = nir_pack_64_2x32(&b, nir_channels(&b, constants, 0x3));
va = nir_iadd(&b, va, nir_u2u64(&b, offset));
nir_def *load = nir_build_load_global(&b, 4, 32, va, .align_mul = 16);
nir_def *load = nir_load_global(&b, 4, 32, va, .align_mul = 16);
/* data = (data & ~htile_mask) | (htile_value & htile_mask) */
nir_def *data = nir_iand(&b, load, nir_channel(&b, constants, 3));
@ -1002,7 +1002,7 @@ radv_meta_nir_build_copy_vrs_htile_shader(struct radv_device *device, struct rad
nir_push_if(&b, nir_ieq_imm(&b, read_htile_value, 1));
{
/* Load the existing HTILE 32-bit value for this 8x8 pixels area. */
nir_def *input_value = nir_build_load_global(&b, 1, 32, nir_iadd(&b, htile_va, nir_u2u64(&b, htile_offset)));
nir_def *input_value = nir_load_global(&b, 1, 32, nir_iadd(&b, htile_va, nir_u2u64(&b, htile_offset)));
/* Clear the 4-bit VRS rates. */
nir_store_var(&b, htile_value, nir_iand_imm(&b, input_value, 0xfffff33f), 0x1);

6
src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c
View file

@ -129,7 +129,7 @@ visit_load_vulkan_descriptor(nir_builder *b, apply_layout_state *state, nir_intr
nir_def *addr = convert_pointer_to_64_bit(b, state,
nir_iadd(b, nir_unpack_64_2x32_split_x(b, intrin->src[0].ssa),
nir_unpack_64_2x32_split_y(b, intrin->src[0].ssa)));
nir_def *desc = nir_build_load_global(b, 1, 64, addr, .access = ACCESS_NON_WRITEABLE);
nir_def *desc = nir_load_global(b, 1, 64, addr, .access = ACCESS_NON_WRITEABLE);
nir_def_rewrite_uses(&intrin->def, desc);
} else {
@ -181,8 +181,8 @@ visit_get_ssbo_size(nir_builder *b, apply_layout_state *state, nir_intrinsic_ins
nir_def *ptr = nir_iadd(b, nir_channel(b, rsrc, 0), nir_channel(b, rsrc, 1));
ptr = nir_iadd_imm(b, ptr, 8);
ptr = convert_pointer_to_64_bit(b, state, ptr);
size = nir_build_load_global(b, 4, 32, ptr, .access = ACCESS_NON_WRITEABLE | ACCESS_CAN_REORDER, .align_mul = 16,
.align_offset = 4);
size = nir_load_global(b, 4, 32, ptr, .access = ACCESS_NON_WRITEABLE | ACCESS_CAN_REORDER, .align_mul = 16,
.align_offset = 4);
} else {
/* load the entire descriptor so it can be CSE'd */
nir_def *ptr = convert_pointer_to_64_bit(b, state, nir_channel(b, rsrc, 0));

4
src/amd/vulkan/nir/radv_nir_lower_abi.c
View file

@ -294,8 +294,8 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state)
offset = nir_iadd_imm_nuw(b, offset, sample_pos_offset);
addr = nir_iadd(b, addr, nir_u2u64(b, offset));
replacement = nir_build_load_global(b, 2, 32, addr,
.access = ACCESS_NON_WRITEABLE | ACCESS_CAN_SPECULATE | ACCESS_CAN_REORDER);
replacement =
nir_load_global(b, 2, 32, addr, .access = ACCESS_NON_WRITEABLE | ACCESS_CAN_SPECULATE | ACCESS_CAN_REORDER);
break;
}
case nir_intrinsic_load_rasterization_samples_amd:

6
src/amd/vulkan/nir/radv_nir_lower_ray_queries.c
View file

@ -288,9 +288,9 @@ lower_rq_initialize(nir_builder *b, nir_intrinsic_instr *instr, struct ray_query
nir_def *bvh_offset = NULL;
nir_push_if(b, accel_struct_non_null);
{
bvh_offset = nir_build_load_global(
b, 1, 32, nir_iadd_imm(b, accel_struct, offsetof(struct radv_accel_struct_header, bvh_offset)),
.access = ACCESS_NON_WRITEABLE);
bvh_offset =
nir_load_global(b, 1, 32, nir_iadd_imm(b, accel_struct, offsetof(struct radv_accel_struct_header, bvh_offset)),
.access = ACCESS_NON_WRITEABLE);
}
nir_pop_if(b, NULL);
bvh_offset = nir_if_phi(b, bvh_offset, zero);

70
src/amd/vulkan/nir/radv_nir_rt_common.c
View file

@ -105,14 +105,14 @@ intersect_ray_amd_software_box(struct radv_device *device, nir_builder *b, nir_d
};
/* node->children[i] -> uint */
nir_def *child_index = nir_build_load_global(b, 1, 32, nir_iadd_imm(b, node_addr, child_offset), .align_mul = 64,
.align_offset = child_offset % 64);
nir_def *child_index = nir_load_global(b, 1, 32, nir_iadd_imm(b, node_addr, child_offset), .align_mul = 64,
.align_offset = child_offset % 64);
/* node->coords[i][0], node->coords[i][1] -> vec3 */
nir_def *node_coords[2] = {
nir_build_load_global(b, 3, 32, nir_iadd_imm(b, node_addr, coord_offsets[0]), .align_mul = 64,
.align_offset = coord_offsets[0] % 64),
nir_build_load_global(b, 3, 32, nir_iadd_imm(b, node_addr, coord_offsets[1]), .align_mul = 64,
.align_offset = coord_offsets[1] % 64),
nir_load_global(b, 3, 32, nir_iadd_imm(b, node_addr, coord_offsets[0]), .align_mul = 64,
.align_offset = coord_offsets[0] % 64),
nir_load_global(b, 3, 32, nir_iadd_imm(b, node_addr, coord_offsets[1]), .align_mul = 64,
.align_offset = coord_offsets[1] % 64),
};
/* If x of the aabb min is NaN, then this is an inactive aabb.
@ -209,12 +209,12 @@ intersect_ray_amd_software_tri(struct radv_device *device, nir_builder *b, nir_d
/* node->coords[0], node->coords[1], node->coords[2] -> vec3 */
nir_def *node_coords[3] = {
nir_build_load_global(b, 3, 32, nir_iadd_imm(b, node_addr, coord_offsets[0]), .align_mul = 64,
.align_offset = coord_offsets[0] % 64),
nir_build_load_global(b, 3, 32, nir_iadd_imm(b, node_addr, coord_offsets[1]), .align_mul = 64,
.align_offset = coord_offsets[1] % 64),
nir_build_load_global(b, 3, 32, nir_iadd_imm(b, node_addr, coord_offsets[2]), .align_mul = 64,
.align_offset = coord_offsets[2] % 64),
nir_load_global(b, 3, 32, nir_iadd_imm(b, node_addr, coord_offsets[0]), .align_mul = 64,
.align_offset = coord_offsets[0] % 64),
nir_load_global(b, 3, 32, nir_iadd_imm(b, node_addr, coord_offsets[1]), .align_mul = 64,
.align_offset = coord_offsets[1] % 64),
nir_load_global(b, 3, 32, nir_iadd_imm(b, node_addr, coord_offsets[2]), .align_mul = 64,
.align_offset = coord_offsets[2] % 64),
};
nir_variable *result = nir_variable_create(b->shader, nir_var_shader_temp, vec4_type, "result");
@ -441,7 +441,7 @@ radv_load_vertex_position(struct radv_device *device, nir_builder *b, nir_def *p
uint32_t offset = ROUND_DOWN_TO(RADV_GFX12_PRIMITIVE_NODE_HEADER_SIZE / 8, 4) + index * 3 * sizeof(float);
nir_def *data[4];
for (uint32_t i = 0; i < ARRAY_SIZE(data); i++) {
data[i] = nir_build_load_global(b, 1, 32, nir_iadd_imm(b, primitive_addr, offset));
data[i] = nir_load_global(b, 1, 32, nir_iadd_imm(b, primitive_addr, offset));
offset += 4;
}
@ -458,7 +458,7 @@ radv_load_vertex_position(struct radv_device *device, nir_builder *b, nir_def *p
}
uint32_t offset = index * 3 * sizeof(float);
return nir_build_load_global(b, 3, 32, nir_iadd_imm(b, primitive_addr, offset));
return nir_load_global(b, 3, 32, nir_iadd_imm(b, primitive_addr, offset));
}
void
@ -471,8 +471,8 @@ radv_load_wto_matrix(struct radv_device *device, nir_builder *b, nir_def *instan
offset = offsetof(struct radv_gfx12_instance_node, wto_matrix);
for (unsigned i = 0; i < 3; ++i) {
out[i] = nir_build_load_global(b, 4, 32, nir_iadd_imm(b, instance_addr, offset + i * 16), .align_mul = 64,
.align_offset = (offset + i * 16) % 64);
out[i] = nir_load_global(b, 4, 32, nir_iadd_imm(b, instance_addr, offset + i * 16), .align_mul = 64,
.align_offset = (offset + i * 16) % 64);
}
}
@ -487,8 +487,8 @@ radv_load_otw_matrix(struct radv_device *device, nir_builder *b, nir_def *instan
sizeof(struct radv_gfx12_instance_node) + offsetof(struct radv_gfx12_instance_node_user_data, otw_matrix);
for (unsigned i = 0; i < 3; ++i) {
out[i] = nir_build_load_global(b, 4, 32, nir_iadd_imm(b, instance_addr, offset + i * 16), .align_mul = 64,
.align_offset = (offset + i * 16) % 64);
out[i] = nir_load_global(b, 4, 32, nir_iadd_imm(b, instance_addr, offset + i * 16), .align_mul = 64,
.align_offset = (offset + i * 16) % 64);
}
}
@ -498,16 +498,15 @@ radv_load_custom_instance(struct radv_device *device, nir_builder *b, nir_def *i
const struct radv_physical_device *pdev = radv_device_physical(device);
if (radv_use_bvh8(pdev)) {
return nir_build_load_global(
b, 1, 32,
nir_iadd_imm(b, instance_addr,
sizeof(struct radv_gfx12_instance_node) +
offsetof(struct radv_gfx12_instance_node_user_data, custom_instance)));
return nir_load_global(b, 1, 32,
nir_iadd_imm(b, instance_addr,
sizeof(struct radv_gfx12_instance_node) +
offsetof(struct radv_gfx12_instance_node_user_data, custom_instance)));
}
return nir_iand_imm(
b,
nir_build_load_global(
nir_load_global(
b, 1, 32, nir_iadd_imm(b, instance_addr, offsetof(struct radv_bvh_instance_node, custom_instance_and_mask))),
0xFFFFFF);
}
@ -518,15 +517,14 @@ radv_load_instance_id(struct radv_device *device, nir_builder *b, nir_def *insta
const struct radv_physical_device *pdev = radv_device_physical(device);
if (radv_use_bvh8(pdev)) {
return nir_build_load_global(
b, 1, 32,
nir_iadd_imm(b, instance_addr,
sizeof(struct radv_gfx12_instance_node) +
offsetof(struct radv_gfx12_instance_node_user_data, instance_index)));
return nir_load_global(b, 1, 32,
nir_iadd_imm(b, instance_addr,
sizeof(struct radv_gfx12_instance_node) +
offsetof(struct radv_gfx12_instance_node_user_data, instance_index)));
}
return nir_build_load_global(b, 1, 32,
nir_iadd_imm(b, instance_addr, offsetof(struct radv_bvh_instance_node, instance_id)));
return nir_load_global(b, 1, 32,
nir_iadd_imm(b, instance_addr, offsetof(struct radv_bvh_instance_node, instance_id)));
}
/* When a hit is opaque the any_hit shader is skipped for this hit and the hit
@ -630,7 +628,7 @@ insert_traversal_triangle_case(struct radv_device *device, nir_builder *b, const
nir_flt(b, args->tmin, intersection.t), not_cull));
{
intersection.base.node_addr = build_node_to_addr(device, b, bvh_node, false);
nir_def *triangle_info = nir_build_load_global(
nir_def *triangle_info = nir_load_global(
b, 2, 32,
nir_iadd_imm(b, intersection.base.node_addr, offsetof(struct radv_bvh_triangle_node, triangle_id)));
intersection.base.primitive_id = nir_channel(b, triangle_info, 0);
@ -727,7 +725,7 @@ insert_traversal_aabb_case(struct radv_device *device, nir_builder *b, const str
{
struct radv_leaf_intersection intersection;
intersection.node_addr = build_node_to_addr(device, b, bvh_node, false);
nir_def *triangle_info = nir_build_load_global(
nir_def *triangle_info = nir_load_global(
b, 2, 32, nir_iadd_imm(b, intersection.node_addr, offsetof(struct radv_bvh_aabb_node, primitive_id)));
intersection.primitive_id = nir_channel(b, triangle_info, 0);
intersection.geometry_id_and_flags = nir_channel(b, triangle_info, 1);
@ -768,7 +766,7 @@ fetch_parent_node(struct radv_device *device, nir_builder *b, nir_def *bvh, nir_
{
const struct radv_physical_device *pdev = radv_device_physical(device);
nir_def *offset = nir_iadd_imm(b, nir_imul_imm(b, nir_udiv_imm(b, node, radv_use_bvh8(pdev) ? 16 : 8), 4), 4);
return nir_build_load_global(b, 1, 32, nir_isub(b, bvh, nir_u2u64(b, offset)), .align_mul = 4);
return nir_load_global(b, 1, 32, nir_isub(b, bvh, nir_u2u64(b, offset)), .align_mul = 4);
}
static nir_def *
@ -979,7 +977,7 @@ radv_build_ray_traversal(struct radv_device *device, nir_builder *b, const struc
nir_store_deref(b, args->vars.instance_addr, instance_node_addr, 1);
nir_def *instance_data =
nir_build_load_global(b, 4, 32, instance_node_addr, .align_mul = 64, .align_offset = 0);
nir_load_global(b, 4, 32, instance_node_addr, .align_mul = 64, .align_offset = 0);
nir_def *wto_matrix[3];
radv_load_wto_matrix(device, b, instance_node_addr, wto_matrix);
@ -1211,7 +1209,7 @@ radv_build_ray_traversal_gfx12(struct radv_device *device, nir_builder *b, const
(int32_t)offsetof(struct radv_gfx12_box_node, parent_id) - (radv_bvh_node_box32 << 3)));
nir_def *offset = nir_iadd(b, nir_ishl_imm(b, prev, 3), field_offset);
nir_def *bvh_addr = build_node_to_addr(device, b, nir_load_deref(b, args->vars.bvh_base), true);
loaded_parent_id = nir_build_load_global(b, 1, 32, nir_iadd(b, bvh_addr, nir_u2u64(b, offset)));
loaded_parent_id = nir_load_global(b, 1, 32, nir_iadd(b, bvh_addr, nir_u2u64(b, offset)));
}
nir_push_else(b, NULL);
{

18
src/amd/vulkan/nir/radv_nir_rt_shader.c
View file

@ -381,10 +381,10 @@ load_sbt_entry(nir_builder *b, const struct rt_variables *vars, nir_def *idx, en
if (offset == SBT_RECURSIVE_PTR) {
nir_store_var(b, vars->shader_addr,
nir_build_load_global(b, 1, 64, addr, .access = ACCESS_CAN_REORDER | ACCESS_NON_WRITEABLE), 1);
nir_load_global(b, 1, 64, addr, .access = ACCESS_CAN_REORDER | ACCESS_NON_WRITEABLE), 1);
} else {
nir_store_var(b, vars->idx,
nir_build_load_global(b, 1, 32, addr, .access = ACCESS_CAN_REORDER | ACCESS_NON_WRITEABLE), 1);
nir_store_var(b, vars->idx, nir_load_global(b, 1, 32, addr, .access = ACCESS_CAN_REORDER | ACCESS_NON_WRITEABLE),
1);
}
nir_def *record_addr = nir_iadd_imm(b, addr, RADV_RT_HANDLE_SIZE - offset);
@ -978,9 +978,9 @@ radv_build_end_trace_token(nir_builder *b, struct rt_variables *vars, nir_def *t
dst_addr = nir_iadd_imm(b, dst_addr, 4);
nir_def *instance_id_and_hit_kind =
nir_build_load_global(b, 1, 32,
nir_iadd_imm(b, nir_load_var(b, vars->instance_addr),
offsetof(struct radv_bvh_instance_node, instance_id)));
nir_load_global(b, 1, 32,
nir_iadd_imm(b, nir_load_var(b, vars->instance_addr),
offsetof(struct radv_bvh_instance_node, instance_id)));
instance_id_and_hit_kind =
nir_ior(b, instance_id_and_hit_kind, nir_ishl_imm(b, nir_load_var(b, vars->hit_kind), 24));
nir_build_store_global(b, instance_id_and_hit_kind, dst_addr, .align_mul = 4);
@ -1545,9 +1545,9 @@ radv_build_traversal(struct radv_device *device, struct radv_ray_tracing_pipelin
nir_def *bvh_offset;
nir_push_if(b, nir_ine_imm(b, accel_struct, 0));
{
bvh_offset = nir_build_load_global(
b, 1, 32, nir_iadd_imm(b, accel_struct, offsetof(struct radv_accel_struct_header, bvh_offset)),
.access = ACCESS_NON_WRITEABLE);
bvh_offset =
nir_load_global(b, 1, 32, nir_iadd_imm(b, accel_struct, offsetof(struct radv_accel_struct_header, bvh_offset)),
.access = ACCESS_NON_WRITEABLE);
nir_store_var(b, trav_vars.current_node, nir_imm_int(b, RADV_BVH_ROOT_NODE), 0x1);
}
nir_push_else(b, NULL);

2
src/amd/vulkan/radv_debug_nir.c
View file

@ -470,7 +470,7 @@ radv_build_is_valid_va(nir_builder *b, nir_def *addr)
nir_def *index = nir_u2u32(b, nir_udiv_imm(b, masked_addr, RADV_VA_VALIDATION_GRANULARITY_BYTES));
nir_def *offset = nir_imul_imm(b, nir_udiv_imm(b, index, 32), 4);
nir_def *dword =
nir_build_load_global(b, 1, 32, nir_iadd_imm(b, nir_u2u64(b, offset), device->valid_vas_addr), .align_mul = 4);
nir_load_global(b, 1, 32, nir_iadd_imm(b, nir_u2u64(b, offset), device->valid_vas_addr), .align_mul = 4);
index = nir_umod_imm(b, index, 32);
then_valid = nir_bitnz(b, dword, index);
}

73
src/amd/vulkan/radv_dgc.c
View file

@ -839,7 +839,7 @@ dgc_load_ies_va(struct dgc_cmdbuf *cs, nir_def *stream_addr)
nir_def *offset = nir_imm_int(b, layout->vk.ies_src_offset_B);
nir_def *ies_index =
nir_build_load_global(b, 1, 32, nir_iadd(b, stream_addr, nir_u2u64(b, offset)), .access = ACCESS_NON_WRITEABLE);
nir_load_global(b, 1, 32, nir_iadd(b, stream_addr, nir_u2u64(b, offset)), .access = ACCESS_NON_WRITEABLE);
nir_def *ies_stride = load_param32(b, ies_stride);
nir_def *ies_offset = nir_imul(b, ies_index, ies_stride);
@ -1455,8 +1455,8 @@ dgc_emit_draw(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_def *sequence_id)
const struct radv_indirect_command_layout *layout = cs->layout;
nir_builder *b = cs->b;
nir_def *draw_data0 = nir_build_load_global(b, 4, 32, nir_iadd_imm(b, stream_addr, layout->vk.draw_src_offset_B),
.access = ACCESS_NON_WRITEABLE);
nir_def *draw_data0 = nir_load_global(b, 4, 32, nir_iadd_imm(b, stream_addr, layout->vk.draw_src_offset_B),
.access = ACCESS_NON_WRITEABLE);
nir_def *vertex_count = nir_channel(b, draw_data0, 0);
nir_def *instance_count = nir_channel(b, draw_data0, 1);
nir_def *vertex_offset = nir_channel(b, draw_data0, 2);
@ -1481,11 +1481,11 @@ dgc_emit_draw_indexed(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_def *sequ
const struct radv_indirect_command_layout *layout = cs->layout;
nir_builder *b = cs->b;
nir_def *draw_data0 = nir_build_load_global(b, 4, 32, nir_iadd_imm(b, stream_addr, layout->vk.draw_src_offset_B),
.access = ACCESS_NON_WRITEABLE);
nir_def *draw_data0 = nir_load_global(b, 4, 32, nir_iadd_imm(b, stream_addr, layout->vk.draw_src_offset_B),
.access = ACCESS_NON_WRITEABLE);
nir_def *draw_data1 =
nir_build_load_global(b, 1, 32, nir_iadd_imm(b, nir_iadd_imm(b, stream_addr, layout->vk.draw_src_offset_B), 16),
.access = ACCESS_NON_WRITEABLE);
nir_load_global(b, 1, 32, nir_iadd_imm(b, nir_iadd_imm(b, stream_addr, layout->vk.draw_src_offset_B), 16),
.access = ACCESS_NON_WRITEABLE);
nir_def *index_count = nir_channel(b, draw_data0, 0);
nir_def *instance_count = nir_channel(b, draw_data0, 1);
nir_def *first_index = nir_channel(b, draw_data0, 2);
@ -1515,8 +1515,8 @@ dgc_emit_draw_with_count(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_def *s
nir_def *has_drawid = nir_test_mask(b, vtx_base_sgpr, DGC_USES_DRAWID);
nir_def *has_baseinstance = nir_test_mask(b, vtx_base_sgpr, DGC_USES_BASEINSTANCE);
nir_def *draw_data = nir_build_load_global(b, 4, 32, nir_iadd_imm(b, stream_addr, layout->vk.draw_src_offset_B),
.access = ACCESS_NON_WRITEABLE);
nir_def *draw_data = nir_load_global(b, 4, 32, nir_iadd_imm(b, stream_addr, layout->vk.draw_src_offset_B),
.access = ACCESS_NON_WRITEABLE);
nir_def *va = nir_pack_64_2x32(b, nir_channels(b, draw_data, 0x3));
nir_def *stride = nir_channel(b, draw_data, 2);
nir_def *draw_count = nir_umin(b, load_param32(b, max_draw_count), nir_channel(b, draw_data, 3));
@ -1582,8 +1582,8 @@ dgc_emit_index_buffer(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_variable
const struct radv_physical_device *pdev = radv_device_physical(device);
nir_builder *b = cs->b;
nir_def *data = nir_build_load_global(b, 4, 32, nir_iadd_imm(b, stream_addr, layout->vk.index_src_offset_B),
.access = ACCESS_NON_WRITEABLE);
nir_def *data = nir_load_global(b, 4, 32, nir_iadd_imm(b, stream_addr, layout->vk.index_src_offset_B),
.access = ACCESS_NON_WRITEABLE);
nir_def *index_type = dgc_get_index_type(cs, nir_channel(b, data, 3));
nir_def *index_size = nir_iand_imm(b, nir_ushr(b, nir_imm_int(b, 0x142), nir_imul_imm(b, index_type, 4)), 0xf);
@ -1647,7 +1647,7 @@ dgc_get_upload_sgpr(struct dgc_cmdbuf *cs, nir_def *param_offset, mesa_shader_st
res = load_shader_metadata32(cs, push_const_sgpr);
} else {
nir_def *va = load_param64(b, params_addr);
res = nir_build_load_global(b, 1, 32, nir_iadd(b, va, nir_u2u64(b, nir_iadd_imm(b, param_offset, stage * 12))));
res = nir_load_global(b, 1, 32, nir_iadd(b, va, nir_u2u64(b, nir_iadd_imm(b, param_offset, stage * 12))));
}
return nir_ubfe_imm(b, res, 0, 16);
@ -1664,7 +1664,7 @@ dgc_get_inline_sgpr(struct dgc_cmdbuf *cs, nir_def *param_offset, mesa_shader_st
res = load_shader_metadata32(cs, push_const_sgpr);
} else {
nir_def *va = load_param64(b, params_addr);
res = nir_build_load_global(b, 1, 32, nir_iadd(b, va, nir_u2u64(b, nir_iadd_imm(b, param_offset, stage * 12))));
res = nir_load_global(b, 1, 32, nir_iadd(b, va, nir_u2u64(b, nir_iadd_imm(b, param_offset, stage * 12))));
}
return nir_ubfe_imm(b, res, 16, 16);
@ -1681,7 +1681,7 @@ dgc_get_inline_mask(struct dgc_cmdbuf *cs, nir_def *param_offset, mesa_shader_st
} else {
nir_def *va = load_param64(b, params_addr);
nir_def *reg_info =
nir_build_load_global(b, 2, 32, nir_iadd(b, va, nir_u2u64(b, nir_iadd_imm(b, param_offset, stage * 12 + 4))));
nir_load_global(b, 2, 32, nir_iadd(b, va, nir_u2u64(b, nir_iadd_imm(b, param_offset, stage * 12 + 4))));
return nir_pack_64_2x32(b, nir_channels(b, reg_info, 0x3));
}
}
@ -1755,7 +1755,7 @@ dgc_alloc_push_constant(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_def *se
nir_def *va = load_param64(b, params_addr);
nir_def *pc_offset = nir_iadd(b, params->const_offset, nir_imul_imm(b, cur_idx, 4));
nir_def *data = nir_build_load_global(b, 1, 32, nir_iadd(b, va, nir_u2u64(b, pc_offset)));
nir_def *data = nir_load_global(b, 1, 32, nir_iadd(b, va, nir_u2u64(b, pc_offset)));
nir_def *offset = nir_iadd(b, upload_offset_pc, nir_imul_imm(b, cur_idx, 4));
nir_build_store_global(b, data, nir_iadd(b, cs->va, nir_u2u64(b, offset)), .access = ACCESS_NON_READABLE);
@ -1771,8 +1771,8 @@ dgc_alloc_push_constant(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_def *se
if (layout->sequence_index_mask & (1ull << i)) {
data = sequence_id;
} else {
data = nir_build_load_global(b, 1, 32, nir_iadd_imm(b, stream_addr, layout->push_constant_offsets[i]),
.access = ACCESS_NON_WRITEABLE);
data = nir_load_global(b, 1, 32, nir_iadd_imm(b, stream_addr, layout->push_constant_offsets[i]),
.access = ACCESS_NON_WRITEABLE);
}
nir_def *offset = nir_iadd_imm(b, upload_offset_pc, i * 4);
@ -1814,8 +1814,8 @@ dgc_emit_push_constant_for_stage(struct dgc_cmdbuf *cs, nir_def *stream_addr, ni
if (layout->sequence_index_mask & (1ull << i)) {
data = sequence_id;
} else {
data = nir_build_load_global(b, 1, 32, nir_iadd_imm(b, stream_addr, layout->push_constant_offsets[i]),
.access = ACCESS_NON_WRITEABLE);
data = nir_load_global(b, 1, 32, nir_iadd_imm(b, stream_addr, layout->push_constant_offsets[i]),
.access = ACCESS_NON_WRITEABLE);
}
/* Determine the inline push constant index by counting the number of bits prior to the
@ -2035,8 +2035,8 @@ dgc_emit_vertex_buffer(struct dgc_cmdbuf *cs, nir_def *stream_addr)
nir_push_if(b, vbo_override);
{
nir_def *stream_offset = load_vbo_offset(cs, cur_idx);
nir_def *stream_data = nir_build_load_global(b, 4, 32, nir_iadd(b, stream_addr, nir_u2u64(b, stream_offset)),
.access = ACCESS_NON_WRITEABLE);
nir_def *stream_data = nir_load_global(b, 4, 32, nir_iadd(b, stream_addr, nir_u2u64(b, stream_offset)),
.access = ACCESS_NON_WRITEABLE);
nir_def *va = nir_pack_64_2x32(b, nir_trim_vector(b, stream_data, 2));
nir_def *size = nir_channel(b, stream_data, 2);
@ -2174,8 +2174,8 @@ dgc_emit_dispatch(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_def *sequence
const struct radv_indirect_command_layout *layout = cs->layout;
nir_builder *b = cs->b;
nir_def *dispatch_data = nir_build_load_global(
b, 3, 32, nir_iadd_imm(b, stream_addr, layout->vk.dispatch_src_offset_B), .access = ACCESS_NON_WRITEABLE);
nir_def *dispatch_data = nir_load_global(b, 3, 32, nir_iadd_imm(b, stream_addr, layout->vk.dispatch_src_offset_B),
.access = ACCESS_NON_WRITEABLE);
nir_def *wg_x = nir_channel(b, dispatch_data, 0);
nir_def *wg_y = nir_channel(b, dispatch_data, 1);
nir_def *wg_z = nir_channel(b, dispatch_data, 2);
@ -2278,8 +2278,8 @@ dgc_emit_draw_mesh_tasks_gfx(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_de
const struct radv_physical_device *pdev = radv_device_physical(device);
nir_builder *b = cs->b;
nir_def *draw_data = nir_build_load_global(b, 3, 32, nir_iadd_imm(b, stream_addr, layout->vk.draw_src_offset_B),
.access = ACCESS_NON_WRITEABLE);
nir_def *draw_data = nir_load_global(b, 3, 32, nir_iadd_imm(b, stream_addr, layout->vk.draw_src_offset_B),
.access = ACCESS_NON_WRITEABLE);
nir_def *x = nir_channel(b, draw_data, 0);
nir_def *y = nir_channel(b, draw_data, 1);
nir_def *z = nir_channel(b, draw_data, 2);
@ -2329,8 +2329,8 @@ dgc_emit_draw_mesh_tasks_with_count_gfx(struct dgc_cmdbuf *cs, nir_def *stream_a
nir_def *has_grid_size = nir_test_mask(b, vtx_base_sgpr, DGC_USES_GRID_SIZE);
nir_def *has_drawid = nir_test_mask(b, vtx_base_sgpr, DGC_USES_DRAWID);
nir_def *draw_data = nir_build_load_global(b, 4, 32, nir_iadd_imm(b, stream_addr, layout->vk.draw_src_offset_B),
.access = ACCESS_NON_WRITEABLE);
nir_def *draw_data = nir_load_global(b, 4, 32, nir_iadd_imm(b, stream_addr, layout->vk.draw_src_offset_B),
.access = ACCESS_NON_WRITEABLE);
nir_def *va = nir_pack_64_2x32(b, nir_channels(b, draw_data, 0x3));
nir_def *stride = nir_channel(b, draw_data, 2);
nir_def *draw_count = nir_umin(b, load_param32(b, max_draw_count), nir_channel(b, draw_data, 3));
@ -2443,8 +2443,8 @@ dgc_emit_draw_mesh_tasks_ace(struct dgc_cmdbuf *ace_cs, nir_def *stream_addr)
const struct radv_indirect_command_layout *layout = ace_cs->layout;
nir_builder *b = ace_cs->b;
nir_def *draw_data = nir_build_load_global(b, 3, 32, nir_iadd_imm(b, stream_addr, layout->vk.draw_src_offset_B),
.access = ACCESS_NON_WRITEABLE);
nir_def *draw_data = nir_load_global(b, 3, 32, nir_iadd_imm(b, stream_addr, layout->vk.draw_src_offset_B),
.access = ACCESS_NON_WRITEABLE);
nir_def *x = nir_channel(b, draw_data, 0);
nir_def *y = nir_channel(b, draw_data, 1);
nir_def *z = nir_channel(b, draw_data, 2);
@ -2463,8 +2463,8 @@ dgc_emit_draw_mesh_tasks_with_count_ace(struct dgc_cmdbuf *ace_cs, nir_def *stre
const struct radv_indirect_command_layout *layout = ace_cs->layout;
nir_builder *b = ace_cs->b;
nir_def *draw_data = nir_build_load_global(b, 4, 32, nir_iadd_imm(b, stream_addr, layout->vk.draw_src_offset_B),
.access = ACCESS_NON_WRITEABLE);
nir_def *draw_data = nir_load_global(b, 4, 32, nir_iadd_imm(b, stream_addr, layout->vk.draw_src_offset_B),
.access = ACCESS_NON_WRITEABLE);
nir_def *va_lo = nir_channel(b, draw_data, 0);
nir_def *va_hi = nir_channel(b, draw_data, 1);
nir_def *stride = nir_channel(b, draw_data, 2);
@ -2522,7 +2522,7 @@ dgc_emit_ies(struct dgc_cmdbuf *cs)
nir_builder *b = cs->b;
nir_def *va = nir_iadd_imm(b, cs->ies_va, sizeof(struct radv_compute_pipeline_metadata));
nir_def *num_dw = nir_build_load_global(b, 1, 32, va, .access = ACCESS_NON_WRITEABLE);
nir_def *num_dw = nir_load_global(b, 1, 32, va, .access = ACCESS_NON_WRITEABLE);
nir_def *cs_va = nir_iadd_imm(b, va, 4);
nir_variable *offset = nir_variable_create(b->shader, nir_var_shader_temp, glsl_uint_type(), "offset");
@ -2534,8 +2534,8 @@ dgc_emit_ies(struct dgc_cmdbuf *cs)
nir_break_if(b, nir_uge(b, cur_offset, num_dw));
nir_def *data = nir_build_load_global(b, 1, 32, nir_iadd(b, cs_va, nir_u2u64(b, nir_imul_imm(b, cur_offset, 4))),
.access = ACCESS_NON_WRITEABLE);
nir_def *data = nir_load_global(b, 1, 32, nir_iadd(b, cs_va, nir_u2u64(b, nir_imul_imm(b, cur_offset, 4))),
.access = ACCESS_NON_WRITEABLE);
dgc_cs_begin(cs);
dgc_cs_emit(data);
@ -2597,7 +2597,7 @@ dgc_emit_rt(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_def *sequence_id)
nir_def *dispatch_initiator_rt = nir_bcsel(b, is_wave32, nir_imm_int(b, dispatch_initiator | S_00B800_CS_W32_EN(1)),
nir_imm_int(b, dispatch_initiator));
nir_def *dispatch_data = nir_build_load_global(b, 3, 32, launch_size_va, .access = ACCESS_NON_WRITEABLE);
nir_def *dispatch_data = nir_load_global(b, 3, 32, launch_size_va, .access = ACCESS_NON_WRITEABLE);
nir_def *width = nir_channel(b, dispatch_data, 0);
nir_def *height = nir_channel(b, dispatch_data, 1);
nir_def *depth = nir_channel(b, dispatch_data, 2);
@ -2884,8 +2884,7 @@ build_dgc_prepare_shader(struct radv_device *dev, struct radv_indirect_command_l
nir_push_if(&b, nir_ine_imm(&b, sequence_count_addr, 0));
{
nir_def *cnt =
nir_build_load_global(&b, 1, 32, load_param64(&b, sequence_count_addr), .access = ACCESS_NON_WRITEABLE);
nir_def *cnt = nir_load_global(&b, 1, 32, load_param64(&b, sequence_count_addr), .access = ACCESS_NON_WRITEABLE);
/* Must clamp count against the API count explicitly.
* The workgroup potentially contains more threads than maxSequencesCount from API,

47
src/amd/vulkan/radv_query.c
View file

@ -241,8 +241,8 @@ build_occlusion_query_shader(struct radv_device *device)
nir_scoped_memory_barrier(&b, SCOPE_INVOCATION, NIR_MEMORY_ACQUIRE, nir_var_mem_ssbo);
nir_def *load_offset = nir_iadd_imm(&b, input_base, rb_avail_offset);
nir_def *load = nir_build_load_global(&b, 1, 32, nir_iadd(&b, src_va, nir_u2u64(&b, load_offset)),
.align_mul = 4, .access = ACCESS_COHERENT);
nir_def *load = nir_load_global(&b, 1, 32, nir_iadd(&b, src_va, nir_u2u64(&b, load_offset)), .align_mul = 4,
.access = ACCESS_COHERENT);
nir_break_if(&b, nir_ige_imm(&b, load, 0x80000000));
}
@ -263,7 +263,7 @@ build_occlusion_query_shader(struct radv_device *device)
nir_def *load_offset = nir_imul_imm(&b, current_outer_count, 16);
load_offset = nir_iadd(&b, input_base, load_offset);
nir_def *load = nir_build_load_global(&b, 2, 64, nir_iadd(&b, src_va, nir_u2u64(&b, load_offset)), .align_mul = 16);
nir_def *load = nir_load_global(&b, 2, 64, nir_iadd(&b, src_va, nir_u2u64(&b, load_offset)), .align_mul = 16);
nir_store_var(&b, start, nir_channel(&b, load, 0), 0x1);
nir_store_var(&b, end, nir_channel(&b, load, 1), 0x1);
@ -494,7 +494,7 @@ build_pipeline_statistics_query_shader(struct radv_device *device)
avail_offset = nir_iadd(&b, avail_offset, nir_imul_imm(&b, global_id, 4));
nir_def *available32 = nir_build_load_global(&b, 1, 32, nir_iadd(&b, src_va, nir_u2u64(&b, avail_offset)));
nir_def *available32 = nir_load_global(&b, 1, 32, nir_iadd(&b, src_va, nir_u2u64(&b, avail_offset)));
nir_store_var(&b, available, nir_i2b(&b, available32), 0x1);
if (pdev->emulate_mesh_shader_queries) {
@ -503,12 +503,11 @@ build_pipeline_statistics_query_shader(struct radv_device *device)
const uint32_t idx = ffs(VK_QUERY_PIPELINE_STATISTIC_TASK_SHADER_INVOCATIONS_BIT_EXT) - 1;
nir_def *avail_start_offset = nir_iadd_imm(&b, input_base, pipeline_statistics_indices[idx] * 8 + 4);
nir_def *avail_start =
nir_build_load_global(&b, 1, 32, nir_iadd(&b, src_va, nir_u2u64(&b, avail_start_offset)));
nir_def *avail_start = nir_load_global(&b, 1, 32, nir_iadd(&b, src_va, nir_u2u64(&b, avail_start_offset)));
nir_def *avail_end_offset =
nir_iadd_imm(&b, input_base, pipeline_statistics_indices[idx] * 8 + pipelinestat_block_size + 4);
nir_def *avail_end = nir_build_load_global(&b, 1, 32, nir_iadd(&b, src_va, nir_u2u64(&b, avail_end_offset)));
nir_def *avail_end = nir_load_global(&b, 1, 32, nir_iadd(&b, src_va, nir_u2u64(&b, avail_end_offset)));
nir_def *task_invoc_result_available =
nir_i2b(&b, nir_iand_imm(&b, nir_iand(&b, avail_start, avail_end), 0x80000000));
@ -532,10 +531,10 @@ build_pipeline_statistics_query_shader(struct radv_device *device)
nir_push_if(&b, nir_test_mask(&b, stats_mask, BITFIELD64_BIT(i)));
nir_def *start_offset = nir_iadd_imm(&b, input_base, pipeline_statistics_indices[i] * 8);
nir_def *start = nir_build_load_global(&b, 1, 64, nir_iadd(&b, src_va, nir_u2u64(&b, start_offset)));
nir_def *start = nir_load_global(&b, 1, 64, nir_iadd(&b, src_va, nir_u2u64(&b, start_offset)));
nir_def *end_offset = nir_iadd_imm(&b, input_base, pipeline_statistics_indices[i] * 8 + pipelinestat_block_size);
nir_def *end = nir_build_load_global(&b, 1, 64, nir_iadd(&b, src_va, nir_u2u64(&b, end_offset)));
nir_def *end = nir_load_global(&b, 1, 64, nir_iadd(&b, src_va, nir_u2u64(&b, end_offset)));
nir_store_var(&b, result, nir_isub(&b, end, start), 0x1);
@ -545,10 +544,10 @@ build_pipeline_statistics_query_shader(struct radv_device *device)
{
/* Compute the emulated result if needed. */
nir_def *emu_start_offset = nir_iadd_imm(&b, input_base, pipelinestat_block_size * 2);
nir_def *emu_start = nir_build_load_global(&b, 1, 64, nir_iadd(&b, src_va, nir_u2u64(&b, emu_start_offset)));
nir_def *emu_start = nir_load_global(&b, 1, 64, nir_iadd(&b, src_va, nir_u2u64(&b, emu_start_offset)));
nir_def *emu_end_offset = nir_iadd_imm(&b, input_base, pipelinestat_block_size * 2 + 8);
nir_def *emu_end = nir_build_load_global(&b, 1, 64, nir_iadd(&b, src_va, nir_u2u64(&b, emu_end_offset)));
nir_def *emu_end = nir_load_global(&b, 1, 64, nir_iadd(&b, src_va, nir_u2u64(&b, emu_end_offset)));
nir_def *ngg_emu_result = nir_isub(&b, emu_end, emu_start);
@ -878,9 +877,9 @@ build_tfb_query_shader(struct radv_device *device)
nir_def *output_base = nir_imul(&b, output_stride, global_id);
/* Load data from the query pool. */
nir_def *load1 = nir_build_load_global(&b, 4, 32, nir_iadd(&b, src_va, nir_u2u64(&b, input_base)), .align_mul = 32);
nir_def *load2 = nir_build_load_global(
&b, 4, 32, nir_iadd(&b, src_va, nir_u2u64(&b, nir_iadd_imm(&b, input_base, 16))), .align_mul = 16);
nir_def *load1 = nir_load_global(&b, 4, 32, nir_iadd(&b, src_va, nir_u2u64(&b, input_base)), .align_mul = 32);
nir_def *load2 = nir_load_global(&b, 4, 32, nir_iadd(&b, src_va, nir_u2u64(&b, nir_iadd_imm(&b, input_base, 16))),
.align_mul = 16);
/* Check if result is available. */
nir_def *avails[2];
@ -1116,7 +1115,7 @@ build_timestamp_query_shader(struct radv_device *device)
nir_def *output_base = nir_imul(&b, output_stride, global_id);
/* Load data from the query pool. */
nir_def *load = nir_build_load_global(&b, 2, 32, nir_iadd(&b, src_va, nir_u2u64(&b, input_base)), .align_mul = 8);
nir_def *load = nir_load_global(&b, 2, 32, nir_iadd(&b, src_va, nir_u2u64(&b, input_base)), .align_mul = 8);
/* Pack the timestamp. */
nir_def *timestamp;
@ -1263,8 +1262,8 @@ build_pg_query_shader(struct radv_device *device)
nir_def *output_base = nir_imul(&b, output_stride, global_id);
/* Load data from the query pool. */
nir_def *load1 = nir_build_load_global(&b, 2, 32, nir_iadd(&b, src_va, nir_u2u64(&b, input_base)), .align_mul = 32);
nir_def *load2 = nir_build_load_global(
nir_def *load1 = nir_load_global(&b, 2, 32, nir_iadd(&b, src_va, nir_u2u64(&b, input_base)), .align_mul = 32);
nir_def *load2 = nir_load_global(
&b, 2, 32, nir_iadd(&b, src_va, nir_u2u64(&b, nir_iadd(&b, input_base, nir_imm_int(&b, 16)))), .align_mul = 16);
/* Check if result is available. */
@ -1275,9 +1274,9 @@ build_pg_query_shader(struct radv_device *device)
nir_push_if(&b, uses_emulated_queries);
{
nir_def *emu_avail_start = nir_build_load_global(
nir_def *emu_avail_start = nir_load_global(
&b, 1, 32, nir_iadd(&b, src_va, nir_u2u64(&b, nir_iadd_imm(&b, input_base, 36))), .align_mul = 4);
nir_def *emu_avail_end = nir_build_load_global(
nir_def *emu_avail_end = nir_load_global(
&b, 1, 32, nir_iadd(&b, src_va, nir_u2u64(&b, nir_iadd_imm(&b, input_base, 44))), .align_mul = 4);
nir_def *emu_result_available =
nir_i2b(&b, nir_iand_imm(&b, nir_iand(&b, emu_avail_start, emu_avail_end), 0x80000000));
@ -1301,9 +1300,9 @@ build_pg_query_shader(struct radv_device *device)
nir_push_if(&b, uses_emulated_queries);
{
nir_def *emu_start = nir_build_load_global(
nir_def *emu_start = nir_load_global(
&b, 1, 32, nir_iadd(&b, src_va, nir_u2u64(&b, nir_iadd(&b, input_base, nir_imm_int(&b, 32)))), .align_mul = 4);
nir_def *emu_end = nir_build_load_global(
nir_def *emu_end = nir_load_global(
&b, 1, 32, nir_iadd(&b, src_va, nir_u2u64(&b, nir_iadd(&b, input_base, nir_imm_int(&b, 40)))), .align_mul = 4);
nir_def *ngg_emu_result = nir_isub(&b, emu_end, emu_start);
@ -1532,9 +1531,9 @@ build_ms_prim_gen_query_shader(struct radv_device *device)
nir_def *output_base = nir_imul(&b, output_stride, global_id);
/* Load data from the query pool. */
nir_def *load1 = nir_build_load_global(&b, 2, 32, nir_iadd(&b, src_va, nir_u2u64(&b, input_base)), .align_mul = 32);
nir_def *load2 = nir_build_load_global(
&b, 2, 32, nir_iadd(&b, src_va, nir_u2u64(&b, nir_iadd_imm(&b, input_base, 8))), .align_mul = 16);
nir_def *load1 = nir_load_global(&b, 2, 32, nir_iadd(&b, src_va, nir_u2u64(&b, input_base)), .align_mul = 32);
nir_def *load2 =
nir_load_global(&b, 2, 32, nir_iadd(&b, src_va, nir_u2u64(&b, nir_iadd_imm(&b, input_base, 8))), .align_mul = 16);
/* Check if result is available. */
nir_def *avails[2];

2
src/asahi/vulkan/hk_shader.c
View file

@ -399,7 +399,7 @@ lower_load_global_bounded(nir_builder *b, nir_intrinsic_instr *intr)
access |= ACCESS_NON_WRITEABLE | ACCESS_CAN_REORDER;
}
nir_def *val = nir_build_load_global(
nir_def *val = nir_load_global(
b, intr->def.num_components, intr->def.bit_size,
nir_iadd(b, base, nir_u2u64(b, offset)),
.align_mul = nir_intrinsic_align_mul(intr),

4
src/compiler/nir/nir_lower_atomics.c
View file

@ -64,8 +64,8 @@ build_atomic(nir_builder *b, nir_intrinsic_instr *intr)
.access = ACCESS_ATOMIC);
break;
case nir_intrinsic_global_atomic:
load = nir_build_load_global(b, 1, intr->def.bit_size, intr->src[0].ssa,
.access = ACCESS_ATOMIC | ACCESS_COHERENT);
load = nir_load_global(b, 1, intr->def.bit_size, intr->src[0].ssa,
.access = ACCESS_ATOMIC | ACCESS_COHERENT);
break;
default:
UNREACHABLE("unsupported atomic type");

12
src/compiler/nir/nir_lower_shader_calls.c
View file

@ -1347,12 +1347,12 @@ lower_stack_instr_to_scratch(struct nir_builder *b, nir_instr *instr, void *data
nir_def *addr = nir_iadd_imm(b,
nir_load_scratch_base_ptr(b, 1, 64, 1),
nir_intrinsic_base(stack));
data = nir_build_load_global(b,
stack->def.num_components,
stack->def.bit_size,
addr,
.align_mul = nir_intrinsic_align_mul(stack),
.align_offset = nir_intrinsic_align_offset(stack));
data = nir_load_global(b,
stack->def.num_components,
stack->def.bit_size,
addr,
.align_mul = nir_intrinsic_align_mul(stack),
.align_offset = nir_intrinsic_align_offset(stack));
} else {
assert(state->address_format == nir_address_format_32bit_offset);
data = nir_load_scratch(b,

10
src/compiler/nir/nir_lower_ssbo.c
View file

@ -42,11 +42,11 @@ pass(nir_builder *b, nir_intrinsic_instr *intr, void *data)
if (opts && opts->native_loads)
return false;
def = nir_build_load_global(b, intr->def.num_components,
intr->def.bit_size,
calc_address(b, intr, opts),
.align_mul = nir_intrinsic_align_mul(intr),
.align_offset = nir_intrinsic_align_offset(intr));
def = nir_load_global(b, intr->def.num_components,
intr->def.bit_size,
calc_address(b, intr, opts),
.align_mul = nir_intrinsic_align_mul(intr),
.align_offset = nir_intrinsic_align_offset(intr));
break;
case nir_intrinsic_store_ssbo:

4
src/compiler/nir/nir_opt_intrinsics.c
View file

@ -534,8 +534,8 @@ try_opt_atomic_to_load(nir_builder *b, nir_intrinsic_instr *intrin,
.base = nir_intrinsic_base(intrin));
break;
case nir_intrinsic_global_atomic:
def = nir_build_load_global(b, 1, bit_size, intrin->src[0].ssa,
.access = ACCESS_ATOMIC | ACCESS_COHERENT);
def = nir_load_global(b, 1, bit_size, intrin->src[0].ssa,
.access = ACCESS_ATOMIC | ACCESS_COHERENT);
break;
case nir_intrinsic_global_atomic_amd:
def = nir_load_global_amd(b, 1, bit_size, intrin->src[0].ssa, intrin->src[2].ssa,

15
src/freedreno/vulkan/tu_nir_lower_ray_query.cc
View file

@ -545,8 +545,9 @@ fetch_parent_node(nir_builder *b, nir_def *bvh, nir_def *node)
{
nir_def *offset = nir_iadd_imm(b, nir_imul_imm(b, node, 4), 4);
return nir_build_load_global(b, 1, 32, nir_isub(b, nir_pack_64_2x32(b, bvh),
nir_u2u64(b, offset)), .align_mul = 4);
return nir_load_global(
b, 1, 32, nir_isub(b, nir_pack_64_2x32(b, bvh), nir_u2u64(b, offset)),
.align_mul = 4);
}
static nir_def *
@ -789,12 +790,10 @@ build_ray_traversal(nir_builder *b, nir_deref_instr *rq,
offsetof(struct tu_leaf_node, geometry_id));
nir_def *geometry_id_ptr = nir_iadd(b, nir_pack_64_2x32(b, bvh_base),
offset);
nir_def *geometry_id =
nir_build_load_global(b, 1, 32, geometry_id_ptr,
.access = ACCESS_NON_WRITEABLE,
.align_mul = sizeof(struct tu_leaf_node),
.align_offset = offsetof(struct tu_leaf_node,
geometry_id));
nir_def *geometry_id = nir_load_global(
b, 1, 32, geometry_id_ptr, .access = ACCESS_NON_WRITEABLE,
.align_mul = sizeof(struct tu_leaf_node),
.align_offset = offsetof(struct tu_leaf_node, geometry_id));
rqi_store(b, candidate, geometry_id, geometry_id, 1);
nir_push_if(b, nir_test_mask(b, intersection_flags,

8
src/gallium/frontends/lavapipe/lvp_ray_tracing_pipeline.c
View file

@ -233,7 +233,7 @@ lvp_load_sbt_entry(nir_builder *b, nir_def *index,
}
return (struct lvp_sbt_entry) {
.value = nir_build_load_global(b, 1, 32, nir_iadd_imm(b, addr, index_offset)),
.value = nir_load_global(b, 1, 32, nir_iadd_imm(b, addr, index_offset)),
.shader_record_ptr = nir_iadd_imm(b, addr, LVP_RAY_TRACING_GROUP_HANDLE_SIZE),
};
}
@ -930,7 +930,7 @@ lvp_lower_ray_tracing_instr(nir_builder *b, nir_instr *instr, void *data)
break;
case nir_intrinsic_load_ray_instance_custom_index: {
nir_def *instance_node_addr = nir_load_var(b, state->instance_addr);
nir_def *custom_instance_and_mask = nir_build_load_global(
nir_def *custom_instance_and_mask = nir_load_global(
b, 1, 32,
nir_iadd_imm(b, instance_node_addr, offsetof(struct lvp_bvh_instance_node, custom_instance_and_mask)));
def = nir_iand_imm(b, custom_instance_and_mask, 0xFFFFFF);
@ -945,7 +945,7 @@ lvp_lower_ray_tracing_instr(nir_builder *b, nir_instr *instr, void *data)
break;
case nir_intrinsic_load_instance_id: {
nir_def *instance_node_addr = nir_load_var(b, state->instance_addr);
def = nir_build_load_global(
def = nir_load_global(
b, 1, 32, nir_iadd_imm(b, instance_node_addr, offsetof(struct lvp_bvh_instance_node, instance_id)));
break;
}
@ -973,7 +973,7 @@ lvp_lower_ray_tracing_instr(nir_builder *b, nir_instr *instr, void *data)
nir_def *instance_node_addr = nir_load_var(b, state->instance_addr);
nir_def *rows[3];
for (unsigned r = 0; r < 3; ++r)
rows[r] = nir_build_load_global(
rows[r] = nir_load_global(
b, 4, 32,
nir_iadd_imm(b, instance_node_addr, offsetof(struct lvp_bvh_instance_node, otw_matrix) + r * 16));
def = nir_vec3(b, nir_channel(b, rows[0], c), nir_channel(b, rows[1], c), nir_channel(b, rows[2], c));

6
src/gallium/frontends/lavapipe/nir/lvp_nir_lower_ray_queries.c
View file

@ -366,7 +366,7 @@ lower_rq_load(nir_builder *b, nir_def *index, nir_intrinsic_instr *instr,
case nir_ray_query_value_intersection_instance_custom_index: {
nir_def *instance_node_addr = rq_load_var(b, index, intersection->instance_addr);
return nir_iand_imm(b,
nir_build_load_global(b, 1, 32,
nir_load_global(b, 1, 32,
nir_iadd_imm(b, instance_node_addr,
offsetof(struct lvp_bvh_instance_node,
custom_instance_and_mask))),
@ -374,7 +374,7 @@ lower_rq_load(nir_builder *b, nir_def *index, nir_intrinsic_instr *instr,
}
case nir_ray_query_value_intersection_instance_id: {
nir_def *instance_node_addr = rq_load_var(b, index, intersection->instance_addr);
return nir_build_load_global(
return nir_load_global(
b, 1, 32,
nir_iadd_imm(b, instance_node_addr, offsetof(struct lvp_bvh_instance_node, instance_id)));
}
@ -396,7 +396,7 @@ lower_rq_load(nir_builder *b, nir_def *index, nir_intrinsic_instr *instr,
nir_def *instance_node_addr = rq_load_var(b, index, intersection->instance_addr);
nir_def *rows[3];
for (unsigned r = 0; r < 3; ++r)
rows[r] = nir_build_load_global(
rows[r] = nir_load_global(
b, 4, 32,
nir_iadd_imm(b, instance_node_addr,
offsetof(struct lvp_bvh_instance_node, otw_matrix) + r * 16));

8
src/gallium/frontends/lavapipe/nir/lvp_nir_ray_tracing.c
View file

@ -37,7 +37,7 @@ lvp_load_node_data(nir_builder *b, nir_def *addr, nir_def **node_data, uint32_t
if (offset < LVP_BVH_NODE_PREFETCH_SIZE && node_data)
return node_data[offset / 4];
return nir_build_load_global(b, 1, 32, nir_iadd_imm(b, addr, offset));
return nir_load_global(b, 1, 32, nir_iadd_imm(b, addr, offset));
}
void
@ -45,7 +45,7 @@ lvp_load_wto_matrix(nir_builder *b, nir_def *instance_addr, nir_def **node_data,
{
unsigned offset = offsetof(struct lvp_bvh_instance_node, wto_matrix);
for (unsigned i = 0; i < 3; ++i) {
out[i] = nir_build_load_global(b, 4, 32, nir_iadd_imm(b, instance_addr, offset + i * 16));
out[i] = nir_load_global(b, 4, 32, nir_iadd_imm(b, instance_addr, offset + i * 16));
out[i] = nir_vec4(b,
lvp_load_node_data(b, instance_addr, node_data, offset + i * 16 + 0),
lvp_load_node_data(b, instance_addr, node_data, offset + i * 16 + 4),
@ -58,7 +58,7 @@ lvp_load_wto_matrix(nir_builder *b, nir_def *instance_addr, nir_def **node_data,
nir_def *
lvp_load_vertex_position(nir_builder *b, nir_def *primitive_addr, uint32_t index)
{
return nir_build_load_global(b, 3, 32, nir_iadd_imm(b, primitive_addr, index * 3 * sizeof(float)));
return nir_load_global(b, 3, 32, nir_iadd_imm(b, primitive_addr, index * 3 * sizeof(float)));
}
static nir_def *
@ -530,7 +530,7 @@ lvp_build_ray_traversal(nir_builder *b, const struct lvp_ray_traversal_args *arg
nir_def *node_data[LVP_BVH_NODE_PREFETCH_SIZE / 4];
for (uint32_t i = 0; i < ARRAY_SIZE(node_data); i++)
node_data[i] = nir_build_load_global(b, 1, 32, nir_iadd_imm(b, node_addr, i * 4));
node_data[i] = nir_load_global(b, 1, 32, nir_iadd_imm(b, node_addr, i * 4));
nir_def *tmax = nir_load_deref(b, args->vars.tmax);

2
src/intel/compiler/brw/brw_nir_rt_builder.h
View file

@ -43,7 +43,7 @@ static inline nir_def *
brw_nir_rt_load(nir_builder *b, nir_def *addr, unsigned align,
unsigned components, unsigned bit_size)
{
return nir_build_load_global(b, components, bit_size, addr,
return nir_load_global(b, components, bit_size, addr,
.align_mul = align,
.access = is_access_for_builder(b));
}

6
src/vulkan/runtime/vk_meta_copy_fill_update.c
View file

@ -1063,7 +1063,7 @@ build_buffer_to_image_fs(const struct vk_meta_device *meta,
coords = nir_isub(b, coords, img_offs);
nir_def *texel = nir_build_load_global(b,
nir_def *texel = nir_load_global(b,
comp_count, comp_sz, copy_img_buf_addr(b, buf_pfmt, coords),
.align_mul = 1 << (ffs(blk_sz) - 1));
@ -1161,7 +1161,7 @@ build_buffer_to_image_cs(const struct vk_meta_device *meta,
unsigned bit_sz = blk_sz & 1 ? 8 : blk_sz & 2 ? 16 : 32;
unsigned comp_count = blk_sz * 8 / bit_sz;
nir_def *texel = nir_build_load_global(b,
nir_def *texel = nir_load_global(b,
comp_count, bit_sz, copy_img_buf_addr(b, buf_pfmt, copy_id),
.align_mul = 1 << (ffs(blk_sz) - 1));
@ -2369,7 +2369,7 @@ build_copy_buffer_shader(const struct vk_meta_device *meta,
nir_def *src_addr = load_info(b, struct vk_meta_copy_buffer_info, src_addr);
nir_def *dst_addr = nir_load_push_constant(b, 1, 64, nir_imm_int(b, 8));
nir_def *data = nir_build_load_global(b, chunk_comp_count, chunk_bit_size,
nir_def *data = nir_load_global(b, chunk_comp_count, chunk_bit_size,
nir_iadd(b, src_addr, offset),
.align_mul = chunk_bit_size / 8);