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aco: add new addr64 bit to MUBUF instructions on GFX6-GFX7
According to the different ISA docs (and to LLVM), this bit seems to only exists on GFX6-GFX7. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-By: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3432>
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4 changed files with 7 additions and 0 deletions
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@ -311,6 +311,9 @@ void emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction*
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encoding |= (mubuf->lds ? 1 : 0) << 16;
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encoding |= (mubuf->glc ? 1 : 0) << 14;
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encoding |= (mubuf->idxen ? 1 : 0) << 13;
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assert(!mubuf->addr64 || ctx.chip_class <= GFX7);
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if (ctx.chip_class == GFX6 || ctx.chip_class == GFX7)
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encoding |= (mubuf->addr64 ? 1 : 0) << 15;
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encoding |= (mubuf->offen ? 1 : 0) << 12;
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if (ctx.chip_class == GFX8 || ctx.chip_class == GFX9) {
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assert(!mubuf->dlc); /* Device-level coherent is not supported on GFX9 and lower */
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@ -786,6 +786,7 @@ struct MUBUF_instruction : public Instruction {
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uint16_t offset : 12; /* Unsigned byte offset - 12 bit */
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bool offen : 1; /* Supply an offset from VGPR (VADDR) */
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bool idxen : 1; /* Supply an index from VGPR (VADDR) */
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bool addr64 : 1; /* SI, CIK: Address size is 64-bit */
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bool glc : 1; /* globally coherent */
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bool dlc : 1; /* NAVI: device level coherent */
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bool slc : 1; /* system level coherent */
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@ -91,6 +91,7 @@ class Format(Enum):
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return [('unsigned', 'offset', None),
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('bool', 'offen', None),
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('bool', 'idxen', 'false'),
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('bool', 'addr64', 'false'),
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('bool', 'disable_wqm', 'false'),
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('bool', 'glc', 'false'),
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('bool', 'dlc', 'false'),
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@ -236,6 +236,8 @@ static void print_instr_format_specific(struct Instruction *instr, FILE *output)
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fprintf(output, " offen");
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if (mubuf->idxen)
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fprintf(output, " idxen");
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if (mubuf->addr64)
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fprintf(output, " addr64");
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if (mubuf->glc)
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fprintf(output, " glc");
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if (mubuf->dlc)
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