fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-22 15:40:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

freedreno/registers: Small cleanup

Browse source 
Whitespace fix plus move a couple regs that ended split apart from the
rest of the VFD regs.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17317>
This commit is contained in:
Rob Clark 2022-06-30 09:05:18 -07:00 • committed by Marge Bot
parent bc6f1afc79
commit 9e1bf8e7ac
1 changed files with 9 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

17
src/freedreno/registers/adreno/a6xx.xml
View file

@ -2778,12 +2778,12 @@ to upconvert to 32b float internally?
<reg32 offset="0xa002" name="VFD_CONTROL_2">
<bitfield name="REGID_HSRELPATCHID" low="0" high="7" type="a3xx_regid">
<doc>
This is the ID of the current patch within the
subdraw, used to calculate the offset of the
patch within the HS->DS buffers. When a draw is
split into multiple subdraws then this differs
from gl_PrimitiveID on the second, third, etc.
subdraws.
This is the ID of the current patch within the
subdraw, used to calculate the offset of the
patch within the HS->DS buffers. When a draw is
split into multiple subdraws then this differs
from gl_PrimitiveID on the second, third, etc.
subdraws.
</doc>
</bitfield>
<bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/>
@ -2851,6 +2851,9 @@ to upconvert to 32b float internally?
<reg32 offset="0xa0f8" name="VFD_POWER_CNTL" low="0" high="2"/>
<reg32 offset="0xa601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
<array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="8"/>
<!--
Note: this seems to always be paired with another bit in another
block.
@ -2859,8 +2862,6 @@ to upconvert to 32b float internally?
<value value="0" name="THREAD64"/>
<value value="1" name="THREAD128"/>
</enum>
<reg32 offset="0xa601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
<array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="8"/>
<bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes">
<!-- if set to SINGLE, only use 1 concurrent wave on each SP -->