mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-05 13:58:04 +02:00
etnaviv: Update headers from rnndb
Update to rnndb commit 8d7ee714cfe2. Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25714>
This commit is contained in:
Tomeu Vizoso
Marge Bot
parent
af199e0ff0
commit
9e05550888
5 changed files with 203 additions and 83 deletions
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@ -8,11 +8,11 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
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git clone git://0x04.net/rules-ng-ng
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The rules-ng-ng source files this header was generated from are:
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||||
- cmdstream.xml ( 16930 bytes, from 2019-01-04 11:37:39)
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||||
- copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26)
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- common.xml ( 35465 bytes, from 2023-11-13 11:29:31)
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- cmdstream.xml ( 16933 bytes, from 2024-01-19 15:52:43)
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- copyright.xml ( 1597 bytes, from 2022-05-20 05:37:53)
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- common.xml ( 35664 bytes, from 2024-01-19 15:52:43)
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Copyright (C) 2012-2019 by the following authors:
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Copyright (C) 2012-2024 by the following authors:
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- Wladimir J. van der Laan <laanwj@gmail.com>
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- Christian Gmeiner <christian.gmeiner@gmail.com>
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- Lucas Stach <l.stach@pengutronix.de>
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@ -293,7 +293,7 @@ DEALINGS IN THE SOFTWARE.
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#define VIV_FE_DRAW_INDIRECT_HEADER_OP__MASK 0xf8000000
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#define VIV_FE_DRAW_INDIRECT_HEADER_OP__SHIFT 27
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#define VIV_FE_DRAW_INDIRECT_HEADER_OP_DRAW_INDIRECT 0x80000000
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#define VIV_FE_DRAW_INDIRECT_HEADER_UNK8 0x00000100
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#define VIV_FE_DRAW_INDIRECT_HEADER_INDEXED 0x00000100
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#define VIV_FE_DRAW_INDIRECT_HEADER_TYPE__MASK 0x0000000f
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#define VIV_FE_DRAW_INDIRECT_HEADER_TYPE__SHIFT 0
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#define VIV_FE_DRAW_INDIRECT_HEADER_TYPE(x) (((x) << VIV_FE_DRAW_INDIRECT_HEADER_TYPE__SHIFT) & VIV_FE_DRAW_INDIRECT_HEADER_TYPE__MASK)
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@ -8,12 +8,12 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
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git clone git://0x04.net/rules-ng-ng
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The rules-ng-ng source files this header was generated from are:
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- texdesc_3d.xml ( 3183 bytes, from 2018-02-10 13:09:26)
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- copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26)
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- common.xml ( 35465 bytes, from 2023-11-13 11:29:31)
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- common_3d.xml ( 15069 bytes, from 2023-11-13 11:29:31)
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- texdesc_3d.xml ( 3183 bytes, from 2022-05-20 05:37:53)
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- copyright.xml ( 1597 bytes, from 2022-05-20 05:37:53)
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- common.xml ( 35664 bytes, from 2024-01-19 15:52:43)
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- common_3d.xml ( 15069 bytes, from 2024-01-19 15:52:43)
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Copyright (C) 2012-2023 by the following authors:
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Copyright (C) 2012-2024 by the following authors:
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- Wladimir J. van der Laan <laanwj@gmail.com>
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- Christian Gmeiner <christian.gmeiner@gmail.com>
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- Lucas Stach <l.stach@pengutronix.de>
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@ -65,6 +65,7 @@ DEALINGS IN THE SOFTWARE.
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#define chipModel_GC520 0x00000520
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#define chipModel_GC530 0x00000530
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#define chipModel_GC600 0x00000600
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#define chipModel_GC620 0x00000620
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#define chipModel_GC700 0x00000700
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#define chipModel_GC800 0x00000800
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#define chipModel_GC860 0x00000860
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@ -481,5 +482,6 @@ DEALINGS IN THE SOFTWARE.
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#define chipMinorFeatures11_NN_INTERLEVE8 0x00000008
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#define chipMinorFeatures11_TP_REORDER 0x00000010
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#define chipMinorFeatures11_PE_DEPTH_ONLY_OQFIX 0x00000020
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#define chipMinorFeatures12_G2D_DEC400EX 0x00000020
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#endif /* COMMON_XML */
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@ -8,10 +8,10 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
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git clone git://0x04.net/rules-ng-ng
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The rules-ng-ng source files this header was generated from are:
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- isa.xml ( 39261 bytes, from 2023-11-13 11:29:31)
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- copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26)
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- isa.xml ( 39261 bytes, from 2024-01-19 15:52:43)
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- copyright.xml ( 1597 bytes, from 2022-05-20 05:37:53)
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Copyright (C) 2012-2023 by the following authors:
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Copyright (C) 2012-2024 by the following authors:
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- Wladimir J. van der Laan <laanwj@gmail.com>
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- Christian Gmeiner <christian.gmeiner@gmail.com>
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- Lucas Stach <l.stach@pengutronix.de>
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@ -8,17 +8,17 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
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git clone git://0x04.net/rules-ng-ng
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The rules-ng-ng source files this header was generated from are:
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- state.xml ( 28218 bytes, from 2023-11-13 11:29:31)
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- common.xml ( 35465 bytes, from 2023-11-13 11:29:31)
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- common_3d.xml ( 15069 bytes, from 2023-11-13 11:29:31)
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- state_hi.xml ( 34935 bytes, from 2023-11-13 11:29:31)
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- copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26)
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- state_2d.xml ( 52271 bytes, from 2023-09-13 13:37:23)
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- state_3d.xml ( 86123 bytes, from 2023-11-13 12:42:26)
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- state_blt.xml ( 14424 bytes, from 2023-09-13 13:37:23)
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- state_vg.xml ( 5975 bytes, from 2018-02-10 13:09:26)
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- state.xml ( 29355 bytes, from 2024-01-19 15:52:43)
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- common.xml ( 35664 bytes, from 2024-01-19 15:52:43)
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- common_3d.xml ( 15069 bytes, from 2024-01-19 15:52:43)
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- state_hi.xml ( 35854 bytes, from 2024-01-19 15:52:43)
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- copyright.xml ( 1597 bytes, from 2022-05-20 05:37:53)
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- state_2d.xml ( 52271 bytes, from 2024-01-19 15:52:43)
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- state_3d.xml ( 89522 bytes, from 2024-01-19 15:52:43)
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- state_blt.xml ( 14592 bytes, from 2024-01-19 15:52:43)
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- state_vg.xml ( 5975 bytes, from 2022-05-20 05:37:53)
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Copyright (C) 2012-2023 by the following authors:
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Copyright (C) 2012-2024 by the following authors:
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- Wladimir J. van der Laan <laanwj@gmail.com>
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- Christian Gmeiner <christian.gmeiner@gmail.com>
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- Lucas Stach <l.stach@pengutronix.de>
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@ -243,6 +243,8 @@ DEALINGS IN THE SOFTWARE.
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#define VIVS_FE_ROBUSTNESS_UNK007F8 0x000007f8
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#define VIVS_FE_MULTI_CLUSTER_UNK007FC 0x000007fc
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#define VIVS_GL 0x00000000
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#define VIVS_GL_PIPE_SELECT 0x00003800
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@ -284,6 +286,7 @@ DEALINGS IN THE SOFTWARE.
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#define VIVS_GL_FLUSH_CACHE_UNK11 0x00000800
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#define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12 0x00001000
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#define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13 0x00002000
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#define VIVS_GL_FLUSH_CACHE_UNK14 0x00004000
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#define VIVS_GL_FLUSH_MMU 0x00003810
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#define VIVS_GL_FLUSH_MMU_FLUSH_FEMMU 0x00000001
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@ -443,6 +446,18 @@ DEALINGS IN THE SOFTWARE.
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#define VIVS_GL_SECURITY_UNK3904 0x00003904
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#define VIVS_GL_MULTI_CLUSTER_UNK3908 0x00003908
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#define VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__MASK 0x00000007
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#define VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__SHIFT 0
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#define VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0(x) (((x) << VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__SHIFT) & VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__MASK)
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#define VIVS_GL_MULTI_CLUSTER_UNK3910(i0) (0x00003910 + 0x4*(i0))
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#define VIVS_GL_MULTI_CLUSTER_UNK3910__ESIZE 0x00000004
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#define VIVS_GL_MULTI_CLUSTER_UNK3910__LEN 0x00000004
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#define VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__MASK 0x000000ff
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#define VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__SHIFT 0
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#define VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK(x) (((x) << VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__SHIFT) & VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__MASK)
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#define VIVS_GL_NN_CONFIG 0x00003930
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#define VIVS_GL_NN_CONFIG_UNK0__MASK 0x00000003
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#define VIVS_GL_NN_CONFIG_UNK0__SHIFT 0
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@ -467,7 +482,12 @@ DEALINGS IN THE SOFTWARE.
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#define VIVS_GL_TP_CONFIG 0x0000394c
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#define VIVS_GL_UNK03950 0x00003950
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#define VIVS_GL_UNK03A00 0x00003a00
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#define VIVS_GL_UNK03A00_UNK0__MASK 0x00000007
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#define VIVS_GL_UNK03A00_UNK0__SHIFT 0
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#define VIVS_GL_UNK03A00_UNK0(x) (((x) << VIVS_GL_UNK03A00_UNK0__SHIFT) & VIVS_GL_UNK03A00_UNK0__MASK)
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#define VIVS_GL_UNK03A04 0x00003a04
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@ -544,5 +564,12 @@ DEALINGS IN THE SOFTWARE.
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#define VIVS_DUMMY_DUMMY 0x0003fffc
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#define VIVS_WD 0x00000000
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#define VIVS_WD_UNK18404 0x00018404
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#define VIVS_WD_UNK18404_UNK0__MASK 0x00000003
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#define VIVS_WD_UNK18404_UNK0__SHIFT 0
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#define VIVS_WD_UNK18404_UNK0(x) (((x) << VIVS_WD_UNK18404_UNK0__SHIFT) & VIVS_WD_UNK18404_UNK0__MASK)
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#endif /* STATE_XML */
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@ -8,17 +8,17 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
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git clone git://0x04.net/rules-ng-ng
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The rules-ng-ng source files this header was generated from are:
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- state.xml ( 28218 bytes, from 2023-11-13 11:29:31)
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- common.xml ( 35465 bytes, from 2023-11-13 11:29:31)
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- common_3d.xml ( 15069 bytes, from 2023-11-13 11:29:31)
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- state_hi.xml ( 34935 bytes, from 2023-11-13 11:29:31)
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- copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26)
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- state_2d.xml ( 52271 bytes, from 2023-09-13 13:37:23)
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- state_3d.xml ( 86123 bytes, from 2023-11-13 12:42:26)
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- state_blt.xml ( 14424 bytes, from 2023-09-13 13:37:23)
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- state_vg.xml ( 5975 bytes, from 2018-02-10 13:09:26)
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- state.xml ( 29355 bytes, from 2024-01-19 15:52:43)
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- common.xml ( 35664 bytes, from 2024-01-19 15:52:43)
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- common_3d.xml ( 15069 bytes, from 2024-01-19 15:52:43)
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- state_hi.xml ( 35854 bytes, from 2024-01-19 15:52:43)
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- copyright.xml ( 1597 bytes, from 2022-05-20 05:37:53)
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- state_2d.xml ( 52271 bytes, from 2024-01-19 15:52:43)
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- state_3d.xml ( 89522 bytes, from 2024-01-19 15:52:43)
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- state_blt.xml ( 14592 bytes, from 2024-01-19 15:52:43)
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- state_vg.xml ( 5975 bytes, from 2022-05-20 05:37:53)
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Copyright (C) 2012-2023 by the following authors:
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Copyright (C) 2012-2024 by the following authors:
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- Wladimir J. van der Laan <laanwj@gmail.com>
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- Christian Gmeiner <christian.gmeiner@gmail.com>
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- Lucas Stach <l.stach@pengutronix.de>
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@ -130,6 +130,18 @@ DEALINGS IN THE SOFTWARE.
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#define COLOR_OUTPUT_MODE_U16 0x00000004
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#define COLOR_OUTPUT_MODE_I8 0x00000005
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#define COLOR_OUTPUT_MODE_I16 0x00000006
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#define RT_CONFIG_STRIDE__MASK 0x0000ffff
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#define RT_CONFIG_STRIDE__SHIFT 0
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#define RT_CONFIG_STRIDE(x) (((x) << RT_CONFIG_STRIDE__SHIFT) & RT_CONFIG_STRIDE__MASK)
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#define RT_CONFIG_FORMAT__MASK 0x03f00000
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#define RT_CONFIG_FORMAT__SHIFT 20
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#define RT_CONFIG_FORMAT(x) (((x) << RT_CONFIG_FORMAT__SHIFT) & RT_CONFIG_FORMAT__MASK)
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#define RT_CONFIG_TS_MODE__MASK 0x04000000
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#define RT_CONFIG_TS_MODE__SHIFT 26
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#define RT_CONFIG_TS_MODE(x) (((x) << RT_CONFIG_TS_MODE__SHIFT) & RT_CONFIG_TS_MODE__MASK)
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#define RT_CONFIG_UNK27 0x08000000
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#define RT_CONFIG_SUPER_TILED 0x10000000
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#define RT_CONFIG_UNK29 0x20000000
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#define VARYING_NUM_COMPONENTS_VAR0__MASK 0x00000007
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#define VARYING_NUM_COMPONENTS_VAR0__SHIFT 0
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#define VARYING_NUM_COMPONENTS_VAR0(x) (((x) << VARYING_NUM_COMPONENTS_VAR0__SHIFT) & VARYING_NUM_COMPONENTS_VAR0__MASK)
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@ -351,6 +363,8 @@ DEALINGS IN THE SOFTWARE.
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#define VIVS_VS_ICACHE_COUNT 0x00015604
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#define VIVS_VS_MULTI_CLUSTER_UNK15608 0x00015608
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#define VIVS_CL 0x00000000
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#define VIVS_CL_CONFIG 0x00000900
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@ -544,6 +558,8 @@ DEALINGS IN THE SOFTWARE.
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#define VIVS_PA_VS_OUTPUT_COUNT 0x00000aa8
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#define VIVS_PA_MULTI_CLUSTER_UNK00AAC 0x00000aac
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#define VIVS_SE 0x00000000
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#define VIVS_SE_SCISSOR_LEFT 0x00000c00
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@ -606,6 +622,18 @@ DEALINGS IN THE SOFTWARE.
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#define VIVS_PS_END_PC 0x00001000
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#define VIVS_PS_OUTPUT_REG 0x00001004
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#define VIVS_PS_OUTPUT_REG_0__MASK 0x0000007f
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#define VIVS_PS_OUTPUT_REG_0__SHIFT 0
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#define VIVS_PS_OUTPUT_REG_0(x) (((x) << VIVS_PS_OUTPUT_REG_0__SHIFT) & VIVS_PS_OUTPUT_REG_0__MASK)
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#define VIVS_PS_OUTPUT_REG_1__MASK 0x00007f00
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#define VIVS_PS_OUTPUT_REG_1__SHIFT 8
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#define VIVS_PS_OUTPUT_REG_1(x) (((x) << VIVS_PS_OUTPUT_REG_1__SHIFT) & VIVS_PS_OUTPUT_REG_1__MASK)
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#define VIVS_PS_OUTPUT_REG_2__MASK 0x007f0000
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#define VIVS_PS_OUTPUT_REG_2__SHIFT 16
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#define VIVS_PS_OUTPUT_REG_2(x) (((x) << VIVS_PS_OUTPUT_REG_2__SHIFT) & VIVS_PS_OUTPUT_REG_2__MASK)
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#define VIVS_PS_OUTPUT_REG_3__MASK 0x7f000000
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#define VIVS_PS_OUTPUT_REG_3__SHIFT 24
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#define VIVS_PS_OUTPUT_REG_3(x) (((x) << VIVS_PS_OUTPUT_REG_3__SHIFT) & VIVS_PS_OUTPUT_REG_3__MASK)
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#define VIVS_PS_INPUT_COUNT 0x00001008
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#define VIVS_PS_INPUT_COUNT_COUNT__MASK 0x0000001f
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@ -649,11 +677,23 @@ DEALINGS IN THE SOFTWARE.
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#define VIVS_PS_INST_ADDR 0x00001028
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#define VIVS_PS_CONTROL2 0x0000102c
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#define VIVS_PS_CONTROL2_SATURATE_RT4 0x00000080
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#define VIVS_PS_CONTROL2_SATURATE_RT5 0x00008000
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#define VIVS_PS_CONTROL2_SATURATE_RT6 0x00800000
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#define VIVS_PS_CONTROL2_SATURATE_RT7 0x80000000
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#define VIVS_PS_OUTPUT_REG2 0x0000102c
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#define VIVS_PS_OUTPUT_REG2_4__MASK 0x0000007f
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#define VIVS_PS_OUTPUT_REG2_4__SHIFT 0
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#define VIVS_PS_OUTPUT_REG2_4(x) (((x) << VIVS_PS_OUTPUT_REG2_4__SHIFT) & VIVS_PS_OUTPUT_REG2_4__MASK)
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#define VIVS_PS_OUTPUT_REG2_SATURATE_RT4 0x00000080
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#define VIVS_PS_OUTPUT_REG2_5__MASK 0x00007f00
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#define VIVS_PS_OUTPUT_REG2_5__SHIFT 8
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#define VIVS_PS_OUTPUT_REG2_5(x) (((x) << VIVS_PS_OUTPUT_REG2_5__SHIFT) & VIVS_PS_OUTPUT_REG2_5__MASK)
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#define VIVS_PS_OUTPUT_REG2_SATURATE_RT5 0x00008000
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#define VIVS_PS_OUTPUT_REG2_6__MASK 0x007f0000
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#define VIVS_PS_OUTPUT_REG2_6__SHIFT 16
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#define VIVS_PS_OUTPUT_REG2_6(x) (((x) << VIVS_PS_OUTPUT_REG2_6__SHIFT) & VIVS_PS_OUTPUT_REG2_6__MASK)
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#define VIVS_PS_OUTPUT_REG2_SATURATE_RT6 0x00800000
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#define VIVS_PS_OUTPUT_REG2_7__MASK 0x7f000000
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#define VIVS_PS_OUTPUT_REG2_7__SHIFT 24
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#define VIVS_PS_OUTPUT_REG2_7(x) (((x) << VIVS_PS_OUTPUT_REG2_7__SHIFT) & VIVS_PS_OUTPUT_REG2_7__MASK)
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#define VIVS_PS_OUTPUT_REG2_SATURATE_RT7 0x80000000
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#define VIVS_PS_CONTROL_EXT 0x00001030
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#define VIVS_PS_CONTROL_EXT_OUTPUT_MODE0__MASK 0x00000007
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@ -715,6 +755,10 @@ DEALINGS IN THE SOFTWARE.
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#define VIVS_PS_NN_INST_ADDR 0x000010a0
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#define VIVS_PS_UNK10A4 0x000010a4
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#define VIVS_PS_MULTI_CLUSTER_UNK10A8 0x000010a8
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#define VIVS_PS_TP_INST_ADDR 0x000010b8
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#define VIVS_PS_INST_MEM(i0) (0x00006000 + 0x4*(i0))
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@ -1040,11 +1084,13 @@ DEALINGS IN THE SOFTWARE.
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#define VIVS_PE_PIPE_DEPTH_ADDR(i0) (0x00001480 + 0x4*(i0))
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#define VIVS_PE_PIPE_ADDR_UNK01500(i0) (0x00001500 + 0x4*(i0))
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||||
#define VIVS_PE_RT_ADDR_4(i0) (0x00000000 + 0x20*(i0))
|
||||
#define VIVS_PE_RT_ADDR_4__ESIZE 0x00000020
|
||||
#define VIVS_PE_RT_ADDR_4__LEN 0x00000003
|
||||
|
||||
#define VIVS_PE_PIPE_ADDR_UNK01520(i0) (0x00001520 + 0x4*(i0))
|
||||
|
||||
#define VIVS_PE_PIPE_ADDR_UNK01540(i0) (0x00001540 + 0x4*(i0))
|
||||
#define VIVS_PE_RT_ADDR_4_PIPE(i0, i1) (0x00001500 + 0x20*(i0) + 0x4*(i1))
|
||||
#define VIVS_PE_RT_ADDR_4_PIPE__ESIZE 0x00000004
|
||||
#define VIVS_PE_RT_ADDR_4_PIPE__LEN 0x00000003
|
||||
|
||||
#define VIVS_PE_STENCIL_CONFIG_EXT 0x000014a0
|
||||
#define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__MASK 0x000000ff
|
||||
|
|
@ -1121,53 +1167,92 @@ DEALINGS IN THE SOFTWARE.
|
|||
|
||||
#define VIVS_PE_ROBUSTNESS_UNK014C4 0x000014c4
|
||||
|
||||
#define VIVS_PE_UNK01580(i0) (0x00001580 + 0x4*(i0))
|
||||
#define VIVS_PE_UNK01580__ESIZE 0x00000004
|
||||
#define VIVS_PE_UNK01580__LEN 0x00000003
|
||||
#define VIVS_PE_RT_CONFIG_4(i0) (0x00001580 + 0x4*(i0))
|
||||
#define VIVS_PE_RT_CONFIG_4__ESIZE 0x00000004
|
||||
#define VIVS_PE_RT_CONFIG_4__LEN 0x00000003
|
||||
|
||||
#define VIVS_PE_RT_ADDR(i0) (0x00000000 + 0x20*(i0))
|
||||
#define VIVS_PE_RT_ADDR__ESIZE 0x00000020
|
||||
#define VIVS_PE_RT_ADDR__LEN 0x00000008
|
||||
#define VIVS_PE_RT_ADDR_8(i0) (0x00000000 + 0x20*(i0))
|
||||
#define VIVS_PE_RT_ADDR_8__ESIZE 0x00000020
|
||||
#define VIVS_PE_RT_ADDR_8__LEN 0x00000008
|
||||
|
||||
#define VIVS_PE_RT_ADDR_PIPE(i0, i1) (0x00014800 + 0x20*(i0) + 0x4*(i1))
|
||||
#define VIVS_PE_RT_ADDR_PIPE__ESIZE 0x00000004
|
||||
#define VIVS_PE_RT_ADDR_PIPE__LEN 0x00000008
|
||||
#define VIVS_PE_RT_ADDR_8_PIPE(i0, i1) (0x00014800 + 0x20*(i0) + 0x4*(i1))
|
||||
#define VIVS_PE_RT_ADDR_8_PIPE__ESIZE 0x00000004
|
||||
#define VIVS_PE_RT_ADDR_8_PIPE__LEN 0x00000008
|
||||
|
||||
#define VIVS_PE_RT_CONFIG(i0) (0x00014900 + 0x4*(i0))
|
||||
#define VIVS_PE_RT_CONFIG__ESIZE 0x00000004
|
||||
#define VIVS_PE_RT_CONFIG__LEN 0x00000008
|
||||
#define VIVS_PE_RT_CONFIG_STRIDE__MASK 0x0000ffff
|
||||
#define VIVS_PE_RT_CONFIG_STRIDE__SHIFT 0
|
||||
#define VIVS_PE_RT_CONFIG_STRIDE(x) (((x) << VIVS_PE_RT_CONFIG_STRIDE__SHIFT) & VIVS_PE_RT_CONFIG_STRIDE__MASK)
|
||||
#define VIVS_PE_RT_CONFIG_FORMAT__MASK 0x001f0000
|
||||
#define VIVS_PE_RT_CONFIG_FORMAT__SHIFT 16
|
||||
#define VIVS_PE_RT_CONFIG_FORMAT(x) (((x) << VIVS_PE_RT_CONFIG_FORMAT__SHIFT) & VIVS_PE_RT_CONFIG_FORMAT__MASK)
|
||||
#define VIVS_PE_RT_CONFIG_SUPER_TILED 0x04000000
|
||||
#define VIVS_PE_RT_CONFIG_UNK28 0x10000000
|
||||
#define VIVS_PE_RT_CONFIG_8(i0) (0x00014900 + 0x4*(i0))
|
||||
#define VIVS_PE_RT_CONFIG_8__ESIZE 0x00000004
|
||||
#define VIVS_PE_RT_CONFIG_8__LEN 0x00000008
|
||||
|
||||
#define VIVS_PE_HALTI5_UNK14920(i0) (0x00014920 + 0x4*(i0))
|
||||
#define VIVS_PE_HALTI5_UNK14920__ESIZE 0x00000004
|
||||
#define VIVS_PE_HALTI5_UNK14920__LEN 0x00000007
|
||||
#define VIVS_PE_HALTI5_UNK14920_COMPONENTS__MASK 0x000000f0
|
||||
#define VIVS_PE_HALTI5_UNK14920_COMPONENTS__SHIFT 4
|
||||
#define VIVS_PE_HALTI5_UNK14920_COMPONENTS(x) (((x) << VIVS_PE_HALTI5_UNK14920_COMPONENTS__SHIFT) & VIVS_PE_HALTI5_UNK14920_COMPONENTS__MASK)
|
||||
#define VIVS_PE_HALTI5_UNK14920_UNK8 0x00000100
|
||||
#define VIVS_PE_HALTI5_RT_COLORMASK(i0) (0x00014920 + 0x4*(i0))
|
||||
#define VIVS_PE_HALTI5_RT_COLORMASK__ESIZE 0x00000004
|
||||
#define VIVS_PE_HALTI5_RT_COLORMASK__LEN 0x00000007
|
||||
#define VIVS_PE_HALTI5_RT_COLORMASK_COMPONENTS__MASK 0x000000f0
|
||||
#define VIVS_PE_HALTI5_RT_COLORMASK_COMPONENTS__SHIFT 4
|
||||
#define VIVS_PE_HALTI5_RT_COLORMASK_COMPONENTS(x) (((x) << VIVS_PE_HALTI5_RT_COLORMASK_COMPONENTS__SHIFT) & VIVS_PE_HALTI5_RT_COLORMASK_COMPONENTS__MASK)
|
||||
#define VIVS_PE_HALTI5_RT_COLORMASK_OVERWRITE 0x00000100
|
||||
|
||||
#define VIVS_PE_HALTI5_UNK14940(i0) (0x00014940 + 0x4*(i0))
|
||||
#define VIVS_PE_HALTI5_UNK14940__ESIZE 0x00000004
|
||||
#define VIVS_PE_HALTI5_UNK14940__LEN 0x00000007
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_OP(i0) (0x00014940 + 0x4*(i0))
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_OP__ESIZE 0x00000004
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_OP__LEN 0x00000007
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_OP_ALPHA_TEST 0x00000001
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_OP_ALPHA_FUNC__MASK 0x00000070
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_OP_ALPHA_FUNC__SHIFT 4
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_OP_ALPHA_FUNC(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_OP_ALPHA_FUNC__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_OP_ALPHA_FUNC__MASK)
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_OP_ALPHA_REF__MASK 0xffff0000
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_OP_ALPHA_REF__SHIFT 16
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_OP_ALPHA_REF(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_OP_ALPHA_REF__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_OP_ALPHA_REF__MASK)
|
||||
|
||||
#define VIVS_PE_HALTI5_UNK14960(i0) (0x00014960 + 0x4*(i0))
|
||||
#define VIVS_PE_HALTI5_UNK14960__ESIZE 0x00000004
|
||||
#define VIVS_PE_HALTI5_UNK14960__LEN 0x00000007
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG(i0) (0x00014960 + 0x4*(i0))
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG__ESIZE 0x00000004
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG__LEN 0x00000007
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_BLEND_ENABLE_COLOR 0x00000001
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_BLEND_ENABLE_COLOR_MASK 0x00000002
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_COLOR_MASK 0x00000004
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_COLOR_MASK 0x00000008
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_COLOR__MASK 0x000000f0
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_COLOR__SHIFT 4
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_COLOR(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_COLOR__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_COLOR__MASK)
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_COLOR__MASK 0x00000f00
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_COLOR__SHIFT 8
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_COLOR(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_COLOR__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_COLOR__MASK)
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_COLOR__MASK 0x00007000
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_COLOR__SHIFT 12
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_COLOR(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_COLOR__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_COLOR__MASK)
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_COLOR_MASK 0x00008000
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA 0x00010000
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA_MASK 0x00020000
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_ALPHA_MASK 0x00040000
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_ALPHA_MASK 0x00080000
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_ALPHA__MASK 0x00f00000
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_ALPHA__SHIFT 20
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_ALPHA(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_ALPHA__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_ALPHA__MASK)
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_ALPHA__MASK 0x0f000000
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_ALPHA__SHIFT 24
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_ALPHA(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_ALPHA__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_ALPHA__MASK)
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_ALPHA__MASK 0x70000000
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_ALPHA__SHIFT 28
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_ALPHA(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_ALPHA__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_ALPHA__MASK)
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_ALPHA_MASK 0x80000000
|
||||
|
||||
#define VIVS_PE_HALTI5_UNK14980(i0) (0x00014980 + 0x4*(i0))
|
||||
#define VIVS_PE_HALTI5_UNK14980__ESIZE 0x00000004
|
||||
#define VIVS_PE_HALTI5_UNK14980__LEN 0x00000007
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0(i0) (0x00014980 + 0x4*(i0))
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0__ESIZE 0x00000004
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0__LEN 0x00000007
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0_B__MASK 0x0000ffff
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0_B__SHIFT 0
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0_B(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0_B__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0_B__MASK)
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0_G__MASK 0xffff0000
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0_G__SHIFT 16
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0_G(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0_G__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0_G__MASK)
|
||||
|
||||
#define VIVS_PE_HALTI5_UNK149A0(i0) (0x000149a0 + 0x4*(i0))
|
||||
#define VIVS_PE_HALTI5_UNK149A0__ESIZE 0x00000004
|
||||
#define VIVS_PE_HALTI5_UNK149A0__LEN 0x00000007
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1(i0) (0x000149a0 + 0x4*(i0))
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1__ESIZE 0x00000004
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1__LEN 0x00000007
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1_R__MASK 0x0000ffff
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1_R__SHIFT 0
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1_R(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1_R__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1_R__MASK)
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1_A__MASK 0xffff0000
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1_A__SHIFT 16
|
||||
#define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1_A(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1_A__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1_A__MASK)
|
||||
|
||||
#define VIVS_PE_ROBUSTNESS_UNK149C0(i0) (0x000149c0 + 0x4*(i0))
|
||||
#define VIVS_PE_ROBUSTNESS_UNK149C0__ESIZE 0x00000004
|
||||
|
|
@ -1412,7 +1497,13 @@ DEALINGS IN THE SOFTWARE.
|
|||
#define VIVS_TS_RT__ESIZE 0x00000004
|
||||
#define VIVS_TS_RT__LEN 0x00000008
|
||||
|
||||
#define VIVS_TS_RT_UNK017A0(i0) (0x000017a0 + 0x4*(i0))
|
||||
#define VIVS_TS_RT_CONFIG(i0) (0x000017a0 + 0x4*(i0))
|
||||
#define VIVS_TS_RT_CONFIG_ENABLE 0x00000001
|
||||
#define VIVS_TS_RT_CONFIG_COLOR_AUTO_DISABLE 0x00000002
|
||||
#define VIVS_TS_RT_CONFIG_COMPRESSION 0x00000004
|
||||
#define VIVS_TS_RT_CONFIG_COMPRESSION_FORMAT__MASK 0x00000078
|
||||
#define VIVS_TS_RT_CONFIG_COMPRESSION_FORMAT__SHIFT 3
|
||||
#define VIVS_TS_RT_CONFIG_COMPRESSION_FORMAT(x) (((x) << VIVS_TS_RT_CONFIG_COMPRESSION_FORMAT__SHIFT) & VIVS_TS_RT_CONFIG_COMPRESSION_FORMAT__MASK)
|
||||
|
||||
#define VIVS_TS_RT_STATUS_BASE(i0) (0x000017c0 + 0x4*(i0))
|
||||
|
||||
|
|
@ -1422,7 +1513,7 @@ DEALINGS IN THE SOFTWARE.
|
|||
|
||||
#define VIVS_TS_RT_CLEAR_VALUE2(i0) (0x00001a20 + 0x4*(i0))
|
||||
|
||||
#define VIVS_TS_RT_UNK01A40(i0) (0x00001a40 + 0x4*(i0))
|
||||
#define VIVS_TS_RT_COLOR_AUTO_DISABLE_COUNT(i0) (0x00001a40 + 0x4*(i0))
|
||||
|
||||
#define VIVS_YUV 0x00000000
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue