diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
index d3ad3423bac..ce8ca02bf74 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
+++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
@@ -410,11 +410,15 @@ lp_build_fill_mattrs(std::vector<std::string> &MAttrs)
 #endif
 
 #if DETECT_ARCH_RISCV64 == 1
-   /* Before riscv is more matured and util_get_cpu_caps() is implemented,
-    * assume this for now since most of linux capable riscv machine are
-    * riscv64gc
-    */
-   MAttrs = {"+m","+c","+a","+d","+f"};
+   /* Linux currently requires IMA, so hardcode it */
+   MAttrs = {"+m","+a"};
+   MAttrs.push_back(util_get_cpu_caps()->has_rv_fd ? "+f" : "-f");
+   MAttrs.push_back(util_get_cpu_caps()->has_rv_fd ? "+d" : "-d");
+   MAttrs.push_back(util_get_cpu_caps()->has_rv_c ? "+c" : "-c");
+   MAttrs.push_back(util_get_cpu_caps()->has_rv_v ? "+v" : "-v");
+   MAttrs.push_back(util_get_cpu_caps()->has_rv_zba ? "+zba" : "-zba");
+   MAttrs.push_back(util_get_cpu_caps()->has_rv_zbb ? "+zbb" : "-zbb");
+   MAttrs.push_back(util_get_cpu_caps()->has_rv_zbs ? "+zbb" : "-zbs");
 #endif
 
 #if DETECT_ARCH_LOONGARCH64 == 1
diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c b/src/gallium/drivers/llvmpipe/lp_screen.c
index 8b6ab50db00..34b86c39b34 100644
--- a/src/gallium/drivers/llvmpipe/lp_screen.c
+++ b/src/gallium/drivers/llvmpipe/lp_screen.c
@@ -838,11 +838,11 @@ update_cache_sha1_cpu(struct mesa_sha1 *ctx)
    const struct util_cpu_caps_t *cpu_caps = util_get_cpu_caps();
    /*
     * Don't need the cpu cache affinity stuff. The rest
-    * is contained in first 4 dwords.
+    * is contained in first 5 dwords.
     */
    STATIC_ASSERT(offsetof(struct util_cpu_caps_t, num_L3_caches)
-                 == 4 * sizeof(uint32_t));
-   _mesa_sha1_update(ctx, cpu_caps, 4 * sizeof(uint32_t));
+                 == 5 * sizeof(uint32_t));
+   _mesa_sha1_update(ctx, cpu_caps, 5 * sizeof(uint32_t));
 }
 
 
diff --git a/src/util/u_cpu_detect.c b/src/util/u_cpu_detect.c
index fd667697d3a..db261d29c7a 100644
--- a/src/util/u_cpu_detect.c
+++ b/src/util/u_cpu_detect.c
@@ -441,6 +441,15 @@ check_os_loongarch64_support(void)
 }
 #endif /* DETECT_ARCH_LOONGARCH64 */
 
+#if DETECT_ARCH_RISCV
+static void
+check_os_riscv_support(void)
+{
+   /* Stub code assume GC (IMAFDC) */
+   util_cpu_caps.has_rv_fd = 1;
+   util_cpu_caps.has_rv_c = 1;
+}
+#endif
 
 static void
 get_cpu_topology(bool zen)
@@ -886,6 +895,10 @@ _util_cpu_detect_once(void)
    check_os_loongarch64_support();
 #endif /* DETECT_ARCH_LOONGARCH64 */
 
+#if DETECT_ARCH_RISCV
+   check_os_riscv_support();
+#endif /* DETECT_ARCH_RISCV */
+
    check_cpu_caps_override();
 
    /* max_vector_bits should be checked after cpu caps override */
@@ -916,6 +929,12 @@ _util_cpu_detect_once(void)
       printf("util_cpu_caps.has_daz = %u\n", util_cpu_caps.has_daz);
       printf("util_cpu_caps.has_lsx = %u\n", util_cpu_caps.has_lsx);
       printf("util_cpu_caps.has_lasx = %u\n", util_cpu_caps.has_lasx);
+      printf("util_cpu_caps.has_rv_fd = %u\n", util_cpu_caps.has_rv_fd);
+      printf("util_cpu_caps.has_rv_c = %u\n", util_cpu_caps.has_rv_c);
+      printf("util_cpu_caps.has_rv_v = %u\n", util_cpu_caps.has_rv_v);
+      printf("util_cpu_caps.has_rv_zba = %u\n", util_cpu_caps.has_rv_zba);
+      printf("util_cpu_caps.has_rv_zbb = %u\n", util_cpu_caps.has_rv_zbb);
+      printf("util_cpu_caps.has_rv_zbs = %u\n", util_cpu_caps.has_rv_zbs);
       printf("util_cpu_caps.has_avx512f = %u\n", util_cpu_caps.has_avx512f);
       printf("util_cpu_caps.has_avx512dq = %u\n", util_cpu_caps.has_avx512dq);
       printf("util_cpu_caps.has_avx512ifma = %u\n", util_cpu_caps.has_avx512ifma);
diff --git a/src/util/u_cpu_detect.h b/src/util/u_cpu_detect.h
index ef4c38db263..214c0115fe3 100644
--- a/src/util/u_cpu_detect.h
+++ b/src/util/u_cpu_detect.h
@@ -104,6 +104,13 @@ struct util_cpu_caps_t {
 
    unsigned has_clflushopt:1;
 
+   unsigned has_rv_fd:1;
+   unsigned has_rv_c:1;
+   unsigned has_rv_v:1;
+   unsigned has_rv_zba:1;
+   unsigned has_rv_zbb:1;
+   unsigned has_rv_zbs:1;
+
    unsigned num_L3_caches;
    unsigned num_cpu_mask_bits;
    unsigned max_vector_bits;