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ilo: improve media command helpers
They were written for Gen6 but mostly untested. Make them work for Gen7+. Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
This commit is contained in:
Chia-I Wu
parent
a2054af85c
commit
9dd596c99f
1 changed files with 146 additions and 76 deletions
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@ -32,134 +32,169 @@
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#include "intel_winsys.h"
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#include "ilo_common.h"
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#include "ilo_shader.h"
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#include "ilo_builder.h"
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struct gen6_idrt_data {
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const struct ilo_shader_state *cs;
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uint32_t sampler_offset;
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uint32_t binding_table_offset;
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unsigned curbe_size;
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unsigned thread_group_size;
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};
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static inline void
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gen6_MEDIA_VFE_STATE(struct ilo_builder *builder,
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int max_threads, int num_urb_entries,
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int urb_entry_size)
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unsigned curbe_alloc, bool use_slm)
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{
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const uint8_t cmd_len = 8;
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uint32_t dw2, dw4, *dw;
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const unsigned idrt_alloc =
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((ilo_dev_gen(builder->dev) >= ILO_GEN(7.5)) ? 64 : 32) * 32;
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int max_threads;
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uint32_t *dw;
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ILO_DEV_ASSERT(builder->dev, 6, 6);
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ILO_DEV_ASSERT(builder->dev, 7, 7.5);
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dw2 = (max_threads - 1) << 16 |
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num_urb_entries << 8 |
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1 << 7 | /* Reset Gateway Timer */
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1 << 6; /* Bypass Gateway Control */
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max_threads = builder->dev->thread_count;
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dw4 = urb_entry_size << 16 | /* URB Entry Allocation Size */
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480; /* CURBE Allocation Size */
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curbe_alloc = align(curbe_alloc, 32);
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assert(idrt_alloc + curbe_alloc <= builder->dev->urb_size / (use_slm + 1));
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ilo_builder_batch_pointer(builder, cmd_len, &dw);
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dw[0] = GEN6_RENDER_CMD(MEDIA, MEDIA_VFE_STATE) | (cmd_len - 2);
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dw[1] = 0; /* scratch */
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dw[2] = dw2;
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dw[3] = 0; /* MBZ */
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dw[4] = dw4;
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dw[5] = 0; /* scoreboard */
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dw[2] = (max_threads - 1) << GEN6_VFE_DW2_MAX_THREADS__SHIFT |
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0 << GEN6_VFE_DW2_URB_ENTRY_COUNT__SHIFT |
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GEN6_VFE_DW2_RESET_GATEWAY_TIMER |
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GEN6_VFE_DW2_BYPASS_GATEWAY_CONTROL;
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if (ilo_dev_gen(builder->dev) >= ILO_GEN(7))
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dw[2] |= GEN7_VFE_DW2_GPGPU_MODE;
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dw[3] = 0;
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dw[4] = 0 << GEN6_VFE_DW4_URB_ENTRY_SIZE__SHIFT |
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(curbe_alloc / 32);
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dw[5] = 0;
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dw[6] = 0;
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dw[7] = 0;
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}
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static inline void
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gen6_MEDIA_CURBE_LOAD(struct ilo_builder *builder,
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uint32_t buf, int size)
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uint32_t offset, unsigned size)
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{
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const uint8_t cmd_len = 4;
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uint32_t *dw;
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ILO_DEV_ASSERT(builder->dev, 6, 6);
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ILO_DEV_ASSERT(builder->dev, 7, 7.5);
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assert(buf % 32 == 0);
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/* gen6_push_constant_buffer() allocates buffers in 256-bit units */
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size = align(size, 32);
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assert(offset % 32 == 0 && size % 32 == 0);
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/* GPU hangs if size is zero */
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assert(size);
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ilo_builder_batch_pointer(builder, cmd_len, &dw);
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dw[0] = GEN6_RENDER_CMD(MEDIA, MEDIA_CURBE_LOAD) | (cmd_len - 2);
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dw[1] = 0; /* MBZ */
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dw[1] = 0;
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dw[2] = size;
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dw[3] = buf;
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dw[3] = offset;
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}
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static inline void
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gen6_MEDIA_INTERFACE_DESCRIPTOR_LOAD(struct ilo_builder *builder,
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uint32_t offset, int num_ids)
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uint32_t offset, unsigned size)
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{
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const uint8_t cmd_len = 4;
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const unsigned idrt_alloc =
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((ilo_dev_gen(builder->dev) >= ILO_GEN(7.5)) ? 64 : 32) * 32;
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uint32_t *dw;
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ILO_DEV_ASSERT(builder->dev, 6, 6);
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ILO_DEV_ASSERT(builder->dev, 7, 7.5);
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assert(offset % 32 == 0);
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assert(offset % 32 == 0 && size % 32 == 0);
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assert(size && size <= idrt_alloc);
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ilo_builder_batch_pointer(builder, cmd_len, &dw);
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dw[0] = GEN6_RENDER_CMD(MEDIA, MEDIA_INTERFACE_DESCRIPTOR_LOAD) |
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(cmd_len - 2);
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dw[1] = 0; /* MBZ */
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/* every ID has 8 DWords */
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dw[2] = num_ids * 8 * 4;
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dw[1] = 0;
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dw[2] = size;
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dw[3] = offset;
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}
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static inline void
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gen6_MEDIA_GATEWAY_STATE(struct ilo_builder *builder,
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int id, int byte, int thread_count)
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gen6_MEDIA_STATE_FLUSH(struct ilo_builder *builder)
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{
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const uint8_t cmd_len = 2;
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uint32_t *dw;
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ILO_DEV_ASSERT(builder->dev, 6, 6);
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ilo_builder_batch_pointer(builder, cmd_len, &dw);
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dw[0] = GEN6_RENDER_CMD(MEDIA, MEDIA_GATEWAY_STATE) | (cmd_len - 2);
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dw[1] = id << 16 |
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byte << 8 |
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thread_count;
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}
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static inline void
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gen6_MEDIA_STATE_FLUSH(struct ilo_builder *builder,
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int thread_count_water_mark,
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int barrier_mask)
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{
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const uint8_t cmd_len = 2;
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uint32_t *dw;
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ILO_DEV_ASSERT(builder->dev, 6, 6);
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ILO_DEV_ASSERT(builder->dev, 7, 7.5);
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ilo_builder_batch_pointer(builder, cmd_len, &dw);
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dw[0] = GEN6_RENDER_CMD(MEDIA, MEDIA_STATE_FLUSH) | (cmd_len - 2);
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dw[1] = thread_count_water_mark << 16 |
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barrier_mask;
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dw[1] = 0;
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}
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static inline void
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gen6_MEDIA_OBJECT_WALKER(struct ilo_builder *builder)
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gen7_GPGPU_WALKER(struct ilo_builder *builder,
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const unsigned thread_group_offset[3],
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const unsigned thread_group_dim[3],
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unsigned thread_group_size,
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unsigned simd_size)
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{
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assert(!"MEDIA_OBJECT_WALKER unsupported");
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}
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const uint8_t cmd_len = 11;
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uint32_t right_execmask, bottom_execmask;
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unsigned thread_count;
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uint32_t *dw;
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static inline void
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gen7_GPGPU_WALKER(struct ilo_builder *builder)
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{
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assert(!"GPGPU_WALKER unsupported");
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ILO_DEV_ASSERT(builder->dev, 7, 7.5);
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assert(simd_size == 16 || simd_size == 8);
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thread_count = (thread_group_size + simd_size - 1) / simd_size;
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assert(thread_count <= 64);
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right_execmask = thread_group_size % simd_size;
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if (right_execmask)
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right_execmask = (1 << right_execmask) - 1;
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else
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right_execmask = (1 << simd_size) - 1;
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bottom_execmask = 0xffffffff;
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ilo_builder_batch_pointer(builder, cmd_len, &dw);
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dw[0] = GEN7_RENDER_CMD(MEDIA, GPGPU_WALKER) | (cmd_len - 2);
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dw[1] = 0; /* always first IDRT */
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dw[2] = (thread_count - 1) << GEN7_GPGPU_DW2_THREAD_MAX_X__SHIFT;
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if (simd_size == 16)
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dw[2] |= GEN7_GPGPU_DW2_SIMD_SIZE_SIMD16;
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else
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dw[2] |= GEN7_GPGPU_DW2_SIMD_SIZE_SIMD8;
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dw[3] = thread_group_offset[0];
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dw[4] = thread_group_dim[0];
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dw[5] = thread_group_offset[1];
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dw[6] = thread_group_dim[1];
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dw[7] = thread_group_offset[2];
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dw[8] = thread_group_dim[2];
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dw[9] = right_execmask;
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dw[10] = bottom_execmask;
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}
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static inline uint32_t
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gen6_INTERFACE_DESCRIPTOR_DATA(struct ilo_builder *builder,
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const struct ilo_shader_state **cs,
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uint32_t *sampler_state,
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int *num_samplers,
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uint32_t *binding_table_state,
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int *num_surfaces,
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int num_ids)
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const struct gen6_idrt_data *data,
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int idrt_count)
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{
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/*
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* From the Sandy Bridge PRM, volume 2 part 2, page 34:
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@ -175,25 +210,60 @@ gen6_INTERFACE_DESCRIPTOR_DATA(struct ilo_builder *builder,
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* aligned address of the Interface Descriptor data."
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*/
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const int state_align = 32;
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const int state_len = (32 / 4) * num_ids;
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const int state_len = (32 / 4) * idrt_count;
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uint32_t state_offset, *dw;
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int i;
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ILO_DEV_ASSERT(builder->dev, 6, 6);
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ILO_DEV_ASSERT(builder->dev, 7, 7.5);
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state_offset = ilo_builder_state_pointer(builder,
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state_offset = ilo_builder_dynamic_pointer(builder,
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ILO_BUILDER_ITEM_BLOB, state_align, state_len, &dw);
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for (i = 0; i < num_ids; i++) {
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dw[0] = ilo_shader_get_kernel_offset(cs[i]);
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dw[1] = 1 << 18; /* SPF */
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dw[2] = sampler_state[i] |
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(num_samplers[i] + 3) / 4 << 2;
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dw[3] = binding_table_state[i] |
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num_surfaces[i];
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dw[4] = 0 << 16 | /* CURBE Read Length */
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0; /* CURBE Read Offset */
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dw[5] = 0; /* Barrier ID */
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for (i = 0; i < idrt_count; i++) {
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const struct gen6_idrt_data *idrt = &data[i];
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const struct ilo_shader_state *cs = idrt->cs;
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unsigned sampler_count, bt_size, slm_size;
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sampler_count =
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ilo_shader_get_kernel_param(cs, ILO_KERNEL_SAMPLER_COUNT);
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assert(sampler_count <= 16);
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sampler_count = (sampler_count + 3) / 4;
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bt_size =
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ilo_shader_get_kernel_param(cs, ILO_KERNEL_SURFACE_TOTAL_COUNT);
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if (bt_size > 31)
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bt_size = 31;
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slm_size = ilo_shader_get_kernel_param(cs, ILO_KERNEL_CS_LOCAL_SIZE);
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assert(idrt->curbe_size / 32 <= 63);
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dw[0] = ilo_shader_get_kernel_offset(idrt->cs);
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dw[1] = 0;
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dw[2] = idrt->sampler_offset |
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sampler_count << GEN6_IDRT_DW2_SAMPLER_COUNT__SHIFT;
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dw[3] = idrt->binding_table_offset |
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bt_size << GEN6_IDRT_DW3_BINDING_TABLE_SIZE__SHIFT;
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dw[4] = (idrt->curbe_size / 32) << GEN6_IDRT_DW4_CURBE_READ_LEN__SHIFT |
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0 << GEN6_IDRT_DW4_CURBE_READ_OFFSET__SHIFT;
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if (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) {
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dw[5] = GEN7_IDRT_DW5_ROUNDING_MODE_RTNE;
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if (slm_size) {
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assert(slm_size <= 64 * 1024);
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slm_size = util_next_power_of_two((slm_size + 4095) / 4096);
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dw[5] |= GEN7_IDRT_DW5_BARRIER_ENABLE |
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slm_size << GEN7_IDRT_DW5_SLM_SIZE__SHIFT |
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idrt->thread_group_size <<
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GEN7_IDRT_DW5_THREAD_GROUP_SIZE__SHIFT;
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}
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} else {
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dw[5] = 0;
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}
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dw[6] = 0;
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dw[7] = 0;
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