diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index f3ac2b10f75..65045f1c6a0 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -923,8 +923,6 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline,
          &cb->attachments[binding->index];
 
       struct GENX(BLEND_STATE_ENTRY) entry = {
-         .LogicOpEnable = cb->logic_op_enable,
-
          /* Vulkan specification 1.2.168, VkLogicOp:
           *
           *   "Logical operations are controlled by the logicOpEnable and
@@ -939,8 +937,9 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline,
           *
           *   "Enabling LogicOp and Color Buffer Blending at the same time is
           *    UNDEFINED"
+          *
+          * Above is handled during emit since these states are dynamic.
           */
-         .ColorBufferBlendEnable = !cb->logic_op_enable && a->blend_enable,
          .ColorClampRange = COLORCLAMP_RTFORMAT,
          .PreBlendColorClampEnable = true,
          .PostBlendColorClampEnable = true,
@@ -1006,7 +1005,6 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline,
       GENX(3DSTATE_PS_BLEND_header),
    };
    blend.AlphaToCoverageEnable         = blend_state.AlphaToCoverageEnable;
-   blend.ColorBufferBlendEnable        = bs0.ColorBufferBlendEnable;
    blend.SourceAlphaBlendFactor        = bs0.SourceAlphaBlendFactor;
    blend.DestinationAlphaBlendFactor   = bs0.DestinationAlphaBlendFactor;
    blend.SourceBlendFactor             = bs0.SourceBlendFactor;
diff --git a/src/intel/vulkan/gfx8_cmd_buffer.c b/src/intel/vulkan/gfx8_cmd_buffer.c
index 7ecf5cb6eb1..efbaca326c4 100644
--- a/src/intel/vulkan/gfx8_cmd_buffer.c
+++ b/src/intel/vulkan/gfx8_cmd_buffer.c
@@ -519,7 +519,8 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 
    if ((cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) ||
        BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_LOGIC_OP) ||
-       BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_COLOR_WRITE_ENABLES)) {
+       BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_COLOR_WRITE_ENABLES) ||
+       BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_LOGIC_OP_ENABLE)) {
       const uint8_t color_writes = dyn->cb.color_write_enables;
       const struct anv_cmd_graphics_state *state = &cmd_buffer->state.gfx;
       bool has_writeable_rt =
@@ -533,6 +534,8 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
       struct GENX(3DSTATE_PS_BLEND) ps_blend = {
          GENX(3DSTATE_PS_BLEND_header),
          .HasWriteableRT = has_writeable_rt,
+         .ColorBufferBlendEnable =
+            !dyn->cb.logic_op_enable && dyn->cb.attachments[0].blend_enable,
       };
       GENX(3DSTATE_PS_BLEND_pack)(NULL, ps_blend_dwords, &ps_blend);
       anv_batch_emit_merge(&cmd_buffer->batch, ps_blend_dwords,
@@ -564,6 +567,9 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
                                  (pipeline->color_comp_writes[i] &
                                   VK_COLOR_COMPONENT_B_BIT) == 0,
             .LogicOpFunction   = genX(vk_to_intel_logic_op)[dyn->cb.logic_op],
+            .LogicOpEnable     = dyn->cb.logic_op_enable,
+            .ColorBufferBlendEnable =
+               !dyn->cb.logic_op_enable && dyn->cb.attachments[i].blend_enable,
          };
          GENX(BLEND_STATE_ENTRY_pack)(NULL, dws, &entry);
          dws += GENX(BLEND_STATE_ENTRY_length);