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panfrost: Implement RUN_FRAGMENT2 on the Gallium driver
Added structure pan_fb_state and related logic to store and emit the fragment state. Also, move some temporary registers to non-conflicting ones. Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41081>
This commit is contained in:
Marc Alcala Prieto
Marge Bot
parent
f36ba515d3
commit
9d866a0729
5 changed files with 328 additions and 79 deletions
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@ -1,5 +1,6 @@
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/*
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* Copyright (C) 2023 Collabora Ltd.
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* Copyright (C) 2026 Arm Ltd.
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* SPDX-License-Identifier: MIT
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*/
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@ -68,6 +69,192 @@ csf_update_tiler_oom_ctx(struct cs_builder *b, uint64_t addr)
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b->conf.reg_perm = orig_cb;
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}
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#if PAN_ARCH >= 14
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static void
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init_fragment_state(const struct pan_fb_info *fb, unsigned layer_idx,
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const struct pan_tls_info *tls,
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const struct pan_tiler_context *tiler_ctx,
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const struct pan_ptr framebuffer)
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{
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const int crc_rt = GENX(pan_select_crc_rt)(fb, fb->tile_size);
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const bool has_zs_crc_ext = (fb->zs.view.zs || fb->zs.view.s || crc_rt >= 0);
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const struct pan_clean_tile clean_tile = GENX(pan_get_clean_tile_info)(fb);
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struct pan_fb_state fbd_data = {0};
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pan_pack(&fbd_data.frame_size, FRAME_SIZE, cfg) {
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cfg.width = fb->width;
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cfg.height = fb->height;
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}
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fbd_data.sample_positions = fb->sample_positions;
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pan_pack(&fbd_data.flags1, FRAGMENT_FLAGS_1, cfg) {
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/* The force_samples setting dictates the sample-count that is used
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* for rasterization, and works like D3D11's ForcedSampleCount
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* feature:
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*
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* - If force_samples == 0: Let nr_samples dictate sample count
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* - If force_samples == 1: force single-sampled rasterization
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* - If force_samples >= 1: force multi-sampled rasterization
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*
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* This can be used to read SYSTEM_VALUE_SAMPLE_MASK_IN from the
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* fragment shader, even when performing single-sampled rendering.
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*/
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if (fb->pls_enabled) {
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cfg.sample_count = 4;
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cfg.sample_pattern = pan_sample_pattern(1);
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} else if (!fb->force_samples) {
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cfg.sample_count = fb->nr_samples;
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cfg.sample_pattern = pan_sample_pattern(fb->nr_samples);
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} else if (fb->force_samples == 1) {
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cfg.sample_count = fb->nr_samples;
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cfg.sample_pattern = pan_sample_pattern(1);
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} else {
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cfg.sample_count = 1;
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cfg.sample_pattern = pan_sample_pattern(fb->force_samples);
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}
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cfg.effective_tile_size = fb->tile_size;
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cfg.point_sprite_coord_origin_max_y = fb->sprite_coord_origin;
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cfg.first_provoking_vertex = fb->first_provoking_vertex;
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cfg.render_target_count = MAX2(fb->rt_count, 1);
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cfg.color_buffer_allocation = fb->cbuf_allocation;
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}
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fbd_data.tiler = tiler_ctx->valhall.desc;
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/* internal_layer_index in flags0 is used to select the right
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* primitive list in the tiler context, and frame_arg is the value
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* that's passed to the fragment shader through r62-r63, which we use
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* to pass gl_Layer. Since the layer_idx only takes 8-bits, we might
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* use the extra 56-bits we have in frame_argument to pass other
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* information to the fragment shader at some point.
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*/
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assert(layer_idx >= tiler_ctx->valhall.layer_offset);
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fbd_data.frame_argument = layer_idx;
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pan_pack(&fbd_data.flags0, FRAGMENT_FLAGS_0, cfg) {
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cfg.pre_frame_0 =
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pan_fix_frame_shader_mode(fb->bifrost.pre_post.modes[0],
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pan_clean_tile_write_any_set(clean_tile));
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cfg.pre_frame_1 =
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pan_fix_frame_shader_mode(fb->bifrost.pre_post.modes[1],
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pan_clean_tile_write_any_set(clean_tile));
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cfg.post_frame = fb->bifrost.pre_post.modes[2];
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const unsigned zs_bytes_per_pixel = pan_zsbuf_bytes_per_pixel(fb);
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/* We can interleave HSR if we have space for two ZS tiles in
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* the tile buffer. */
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const unsigned max_zs_tile_size_interleave =
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fb->z_tile_buf_budget >> util_logbase2_ceil(zs_bytes_per_pixel);
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const bool hsr_can_interleave =
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fb->tile_size <= max_zs_tile_size_interleave;
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/* Enabling prepass without interleave is generally not good for
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* performance, so disable HSR in that case. */
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cfg.hsr_prepass_enable = fb->allow_hsr_prepass && hsr_can_interleave;
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cfg.hsr_prepass_interleaving_enable = hsr_can_interleave;
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cfg.hsr_prepass_filter_enable = true;
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cfg.hsr_hierarchical_optimizations_enable = true;
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cfg.internal_layer_index = layer_idx - tiler_ctx->valhall.layer_offset;
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}
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fbd_data.dcd_pointer = fb->bifrost.pre_post.dcds.gpu;
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pan_pack(&fbd_data.flags2, FRAGMENT_FLAGS_2, cfg) {
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cfg.s_clear = fb->zs.clear_value.stencil;
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cfg.s_write_enable = (fb->zs.view.s && !fb->zs.discard.s);
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/* Default to 24 bit depth if there's no surface. */
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cfg.z_internal_format =
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fb->zs.view.zs ? pan_get_z_internal_format(fb->zs.view.zs->format)
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: MALI_Z_INTERNAL_FORMAT_D24;
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cfg.z_write_enable = (fb->zs.view.zs && !fb->zs.discard.z);
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if (crc_rt >= 0) {
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bool *valid = fb->rts[crc_rt].crc_valid;
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bool full = !fb->draw_extent.minx && !fb->draw_extent.miny &&
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fb->draw_extent.maxx == (fb->width - 1) &&
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fb->draw_extent.maxy == (fb->height - 1);
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/* If the CRC was valid it stays valid, if it wasn't, we must
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* ensure the render operation covers the full frame, and
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* clean tiles are pushed to memory. */
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bool new_valid = *valid | (full && pan_clean_tile_write_rt_enabled(
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clean_tile, crc_rt));
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cfg.crc_read_enable = *valid;
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/* If the data is currently invalid, still write CRC
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* data if we are doing a full write, so that it is
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* valid for next time. */
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cfg.crc_write_enable = new_valid;
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*valid = new_valid;
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}
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}
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fbd_data.z_clear = util_bitpack_float(fb->zs.clear_value.depth);
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{
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/* Set the DBD and RTD pointers. Both must be 64-bytes aligned. */
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uint64_t out_gpu_addr =
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framebuffer.gpu + ALIGN_POT(sizeof(struct pan_fb_state), 64);
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if (has_zs_crc_ext) {
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fbd_data.dbd_pointer = out_gpu_addr;
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assert(fbd_data.dbd_pointer % 64 == 0);
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out_gpu_addr += pan_size(ZS_CRC_EXTENSION);
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}
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fbd_data.rtd_pointer = out_gpu_addr;
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assert(fbd_data.rtd_pointer % 64 == 0);
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}
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memcpy(framebuffer.cpu, &fbd_data, sizeof(fbd_data));
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}
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static inline void
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cs_emit_fragment_state(struct cs_builder *b, struct cs_index fbd_ptr)
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{
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cs_load32_to(b, cs_sr_reg32(b, FRAGMENT, FRAME_SIZE), fbd_ptr,
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offsetof(struct pan_fb_state, frame_size));
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cs_load64_to(b, cs_sr_reg64(b, FRAGMENT, SAMPLE_POSITION_ARRAY_POINTER),
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fbd_ptr, offsetof(struct pan_fb_state, sample_positions));
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cs_load32_to(b, cs_sr_reg32(b, FRAGMENT, FLAGS_1), fbd_ptr,
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offsetof(struct pan_fb_state, flags1));
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cs_load32_to(b, cs_sr_reg32(b, FRAGMENT, FLAGS_0), fbd_ptr,
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offsetof(struct pan_fb_state, flags0));
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cs_load32_to(b, cs_sr_reg32(b, FRAGMENT, FLAGS_2), fbd_ptr,
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offsetof(struct pan_fb_state, flags2));
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cs_load32_to(b, cs_sr_reg32(b, FRAGMENT, Z_CLEAR), fbd_ptr,
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offsetof(struct pan_fb_state, z_clear));
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cs_load64_to(b, cs_sr_reg64(b, FRAGMENT, TILER_DESCRIPTOR_POINTER), fbd_ptr,
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offsetof(struct pan_fb_state, tiler));
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cs_load64_to(b, cs_sr_reg64(b, FRAGMENT, RTD_POINTER), fbd_ptr,
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offsetof(struct pan_fb_state, rtd_pointer));
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cs_load64_to(b, cs_sr_reg64(b, FRAGMENT, DBD_POINTER), fbd_ptr,
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offsetof(struct pan_fb_state, dbd_pointer));
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cs_load64_to(b, cs_sr_reg64(b, FRAGMENT, FRAME_ARG), fbd_ptr,
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offsetof(struct pan_fb_state, frame_argument));
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cs_load64_to(b, cs_sr_reg64(b, FRAGMENT, FRAME_SHADER_DCD_POINTER), fbd_ptr,
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offsetof(struct pan_fb_state, dcd_pointer));
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cs_move64_to(b, cs_sr_reg64(b, FRAGMENT, VRS_IMAGE), 0);
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cs_move32_to(b, cs_sr_reg32(b, FRAGMENT, FLAGS_3), 0);
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cs_move32_to(b, cs_sr_reg32(b, FRAGMENT, ITER_TRACE_ID0), 0);
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cs_move32_to(b, cs_sr_reg32(b, FRAGMENT, ITER_TRACE_ID1), 0);
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for (unsigned i = 0; i <= 10; i++)
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cs_move64_to(
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b, cs_reg64(b, MALI_FRAGMENT_SR_IRD_BUFFER_POINTER_0 + i * 2), 0);
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cs_move64_to(b, cs_reg64(b, 50), 0);
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cs_move32_to(b, cs_reg32(b, 53), 0);
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}
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#endif /* PAN_ARCH >= 14 */
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#define FIELD_OFFSET(_name) offsetof(struct pan_csf_tiler_oom_ctx, _name)
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#define FBD_OFFSET(_pass) \
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@ -113,13 +300,14 @@ csf_oom_handler_init(struct panfrost_context *ctx)
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cs_function_def(&b, &handler, handler_ctx) {
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struct cs_index tiler_oom_ctx = cs_reg64(&b, TILER_OOM_CTX_REG);
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struct cs_index counter = cs_reg32(&b, 47);
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struct cs_index zero = cs_reg64(&b, 48);
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struct cs_index flush_id = cs_reg32(&b, 48);
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struct cs_index tiler_ctx = cs_reg64(&b, 50);
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struct cs_index completed_top = cs_reg64(&b, 52);
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struct cs_index completed_bottom = cs_reg64(&b, 54);
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struct cs_index completed_chunks = cs_reg_tuple(&b, 52, 4);
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struct cs_index counter = cs_reg32(&b, 31);
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struct cs_index zero = cs_reg64(&b, 56);
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struct cs_index flush_id = cs_reg32(&b, 58);
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struct cs_index tiler_ctx = cs_reg64(&b, 60);
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struct cs_index completed_top = cs_reg64(&b, 64);
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struct cs_index completed_bottom = cs_reg64(&b, 66);
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struct cs_index completed_chunks = cs_reg_tuple(&b, 64, 4);
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struct cs_index fbd_pointer = cs_sr_reg64(&b, FRAGMENT, FBD_POINTER);
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/* Ensure that the OTHER endpoint is valid */
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#if PAN_ARCH >= 11
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@ -133,12 +321,10 @@ csf_oom_handler_init(struct panfrost_context *ctx)
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cs_load32_to(&b, counter, tiler_oom_ctx, FIELD_OFFSET(counter));
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cs_wait_slot(&b, 0);
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cs_if(&b, MALI_CS_CONDITION_GREATER, counter) {
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cs_load64_to(&b, cs_sr_reg64(&b, FRAGMENT, FBD_POINTER), tiler_oom_ctx,
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FBD_OFFSET(MIDDLE));
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cs_load64_to(&b, fbd_pointer, tiler_oom_ctx, FBD_OFFSET(MIDDLE));
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}
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cs_else(&b) {
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cs_load64_to(&b, cs_sr_reg64(&b, FRAGMENT, FBD_POINTER), tiler_oom_ctx,
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FBD_OFFSET(FIRST));
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cs_load64_to(&b, fbd_pointer, tiler_oom_ctx, FBD_OFFSET(FIRST));
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}
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cs_load32_to(&b, cs_sr_reg32(&b, FRAGMENT, BBOX_MIN), tiler_oom_ctx,
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@ -147,11 +333,18 @@ csf_oom_handler_init(struct panfrost_context *ctx)
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FIELD_OFFSET(bbox_max));
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cs_move64_to(&b, cs_sr_reg64(&b, FRAGMENT, TEM_POINTER), 0);
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cs_move32_to(&b, cs_sr_reg32(&b, FRAGMENT, TEM_ROW_STRIDE), 0);
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#if PAN_ARCH >= 14
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cs_emit_fragment_state(&b, fbd_pointer);
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#endif
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cs_wait_slot(&b, 0);
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/* Run the fragment job and wait */
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cs_select_endpoint_sb(&b, 3);
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#if PAN_ARCH >= 14
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cs_run_fragment2(&b, false, MALI_TILE_RENDER_ORDER_Z_ORDER);
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#else
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cs_run_fragment(&b, false, MALI_TILE_RENDER_ORDER_Z_ORDER);
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#endif
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cs_wait_slot(&b, 3);
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/* Increment counter */
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@ -218,6 +411,21 @@ GENX(csf_cleanup_batch)(struct panfrost_batch *batch)
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panfrost_pool_cleanup(&batch->csf.cs_chunk_pool);
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}
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#if PAN_ARCH >= 14
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static inline struct pan_ptr
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alloc_fbd(struct panfrost_batch *batch)
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{
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const struct pan_desc_alloc_info fbd_layer = {
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.size = ALIGN_POT(sizeof(struct pan_fb_state), 64),
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.align = alignof(struct pan_fb_state),
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.nelems = 1,
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};
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return pan_pool_alloc_desc_aggregate(
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&batch->pool.base, fbd_layer, PAN_DESC(ZS_CRC_EXTENSION),
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PAN_DESC_ARRAY(MAX2(batch->key.nr_cbufs, 1), RENDER_TARGET));
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}
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#else
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static inline struct pan_ptr
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alloc_fbd(struct panfrost_batch *batch)
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{
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@ -225,6 +433,7 @@ alloc_fbd(struct panfrost_batch *batch)
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&batch->pool.base, PAN_DESC(FRAMEBUFFER), PAN_DESC(ZS_CRC_EXTENSION),
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PAN_DESC_ARRAY(MAX2(batch->key.nr_cbufs, 1), RENDER_TARGET));
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}
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#endif /* PAN_ARCH >= 14 */
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int
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GENX(csf_init_batch)(struct panfrost_batch *batch)
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@ -777,6 +986,10 @@ emit_ir_fbd(struct pan_csf_tiler_oom_ctx *ctx, enum pan_rendering_pass pass,
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ir_descs.rts = desc_addr;
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ctx->fbds[pass].gpu |= GENX(pan_emit_fbd)(fb, 0, tls, tiler_ctx, &ir_descs);
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#if PAN_ARCH >= 14
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init_fragment_state(fb, 0, tls, tiler_ctx, ctx->fbds[pass]);
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#endif
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}
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void
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@ -808,6 +1021,10 @@ GENX(csf_emit_fbds)(struct panfrost_batch *batch, struct pan_fb_info *fb,
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batch->framebuffer.gpu |=
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GENX(pan_emit_fbd)(fb, 0, tls, &batch->tiler_ctx, &fb_descs);
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#if PAN_ARCH >= 14
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init_fragment_state(fb, 0, tls, &batch->tiler_ctx, batch->framebuffer);
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#endif
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if (batch->draw_count == 0)
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return;
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@ -892,9 +1109,10 @@ GENX(csf_emit_fragment_job)(struct panfrost_batch *batch,
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cs_vt_end(b, cs_now());
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}
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struct cs_index fbd_pointer = cs_sr_reg64(b, FRAGMENT, FBD_POINTER);
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/* Set up the fragment job */
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cs_move64_to(b, cs_sr_reg64(b, FRAGMENT, FBD_POINTER),
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batch->framebuffer.gpu);
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cs_move64_to(b, fbd_pointer, batch->framebuffer.gpu);
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cs_move32_to(b, cs_sr_reg32(b, FRAGMENT, BBOX_MIN),
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(batch->miny << 16) | batch->minx);
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cs_move32_to(b, cs_sr_reg32(b, FRAGMENT, BBOX_MAX),
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@ -909,13 +1127,19 @@ GENX(csf_emit_fragment_job)(struct panfrost_batch *batch,
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cs_load32_to(b, counter, cs_reg64(b, TILER_OOM_CTX_REG), 0);
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cs_wait_slot(b, 0);
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cs_if(b, MALI_CS_CONDITION_GREATER, counter) {
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cs_move64_to(b, cs_sr_reg64(b, FRAGMENT, FBD_POINTER),
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cs_move64_to(b, fbd_pointer,
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oom_ctx->fbds[PAN_INCREMENTAL_RENDERING_LAST_PASS].gpu);
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}
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}
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/* Run the fragment job and wait */
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#if PAN_ARCH >= 14
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cs_emit_fragment_state(b, fbd_pointer);
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cs_wait_slot(b, 0);
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cs_run_fragment2(b, false, MALI_TILE_RENDER_ORDER_Z_ORDER);
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#else
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cs_run_fragment(b, false, MALI_TILE_RENDER_ORDER_Z_ORDER);
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#endif
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cs_wait_slot(b, 2);
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/* Gather freed heap chunks and add them to the heap context free list
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@ -29,7 +29,8 @@ struct pan_csf_tiler_oom_ctx {
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/* Alternative framebuffer descriptors for incremental rendering */
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struct pan_ptr fbds[PAN_INCREMENTAL_RENDERING_PASS_COUNT];
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/* Bounding Box (Register 42 and 43) */
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/* Bounding Box (Register MALI_FRAGMENT_SR_BBOX_MIN and
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* MALI_FRAGMENT_SR_BBOX_MAX) */
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uint32_t bbox_min;
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uint32_t bbox_max;
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@ -127,4 +128,44 @@ void GENX(csf_emit_write_timestamp)(struct panfrost_batch *batch,
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#endif /* PAN_ARCH >= 10 */
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#if PAN_ARCH >= 14
|
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/* Framebuffer state. Keep this structure 64-byte aligned, since
|
||||
* we want the adjacent ZS_CRC_EXTENSION and RENDER_TARGET descriptors
|
||||
* aligned. */
|
||||
struct pan_fb_state {
|
||||
/** GPU address to the tiler descriptor. */
|
||||
uint64_t tiler;
|
||||
|
||||
/** Frame argument. */
|
||||
uint64_t frame_argument;
|
||||
|
||||
/** An instance of Fragment Flags 0. */
|
||||
struct mali_fragment_flags_0_packed flags0;
|
||||
|
||||
/** An instance of Fragment Flags 2. */
|
||||
struct mali_fragment_flags_2_packed flags2;
|
||||
|
||||
/** Z clear value. */
|
||||
uint32_t z_clear;
|
||||
|
||||
/** GPU address to the draw call descriptors. It may be 0. */
|
||||
uint64_t dcd_pointer;
|
||||
|
||||
/** GPU address to the ZS_CRC_EXTENSION descriptor. It may be 0. */
|
||||
uint64_t dbd_pointer;
|
||||
|
||||
/** GPU address to the RENDER_TARGET descriptors. */
|
||||
uint64_t rtd_pointer;
|
||||
|
||||
/** An instance of Frame Size. */
|
||||
struct mali_frame_size_packed frame_size;
|
||||
|
||||
/** GPU address to the sample position array. */
|
||||
uint64_t sample_positions;
|
||||
|
||||
/** An instance of Fragment Flags 1. */
|
||||
struct mali_fragment_flags_1_packed flags1;
|
||||
} __attribute__((aligned(64)));
|
||||
#endif /* PAN_ARCH >= 14 */
|
||||
|
||||
#endif /* __PAN_CSF_H__ */
|
||||
|
|
|
|||
|
|
@ -580,26 +580,6 @@ pan_cbuf_bytes_per_pixel(const struct pan_fb_info *fb)
|
|||
return sum;
|
||||
}
|
||||
|
||||
static unsigned
|
||||
pan_zsbuf_bytes_per_pixel(const struct pan_fb_info *fb)
|
||||
{
|
||||
unsigned samples = fb->nr_samples;
|
||||
|
||||
const struct pan_image_view *zs_view = fb->zs.view.zs;
|
||||
if (zs_view)
|
||||
samples = zs_view->nr_samples;
|
||||
|
||||
const struct pan_image_view *s_view = fb->zs.view.s;
|
||||
if (s_view)
|
||||
samples = MAX2(samples, s_view->nr_samples);
|
||||
|
||||
/* Depth is always stored in a 32-bit float. Stencil requires depth to
|
||||
* be allocated, but doesn't have it's own budget; it's tied to the
|
||||
* depth buffer.
|
||||
*/
|
||||
return sizeof(float) * samples;
|
||||
}
|
||||
|
||||
/*
|
||||
* Select the largest tile size that fits within the tilebuffer budget.
|
||||
* Formally, maximize (pixels per tile) such that it is a power of two and
|
||||
|
|
@ -1065,27 +1045,6 @@ pan_emit_rt(const struct pan_fb_info *fb, unsigned layer_idx, unsigned idx,
|
|||
*out = desc;
|
||||
}
|
||||
|
||||
#if PAN_ARCH >= 6
|
||||
/* All GPUs starting from Bifrost are affected by issue TSIX-2033:
|
||||
*
|
||||
* Forcing clean_tile_writes breaks INTERSECT readbacks
|
||||
*
|
||||
* To workaround, use the pre-frame shader mode ALWAYS instead of INTERSECT if
|
||||
* clean_tile_write_enable is set on either one of the color, depth or stencil
|
||||
* buffers. Since INTERSECT is a hint that the hardware may ignore, this
|
||||
* cannot affect correctness, only performance. */
|
||||
|
||||
static enum mali_pre_post_frame_shader_mode
|
||||
pan_fix_frame_shader_mode(enum mali_pre_post_frame_shader_mode mode,
|
||||
bool force_clean_tile)
|
||||
{
|
||||
if (force_clean_tile && mode == MALI_PRE_POST_FRAME_SHADER_MODE_INTERSECT)
|
||||
return MALI_PRE_POST_FRAME_SHADER_MODE_ALWAYS;
|
||||
else
|
||||
return mode;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Clean tiles must be written back for AFBC buffers (color, z/s) when either
|
||||
* one of the effective tile size dimension is smaller than the superblock
|
||||
* dimension.
|
||||
|
|
@ -1112,8 +1071,8 @@ GENX(pan_force_clean_write_on)(const struct pan_image *image,
|
|||
#endif
|
||||
}
|
||||
|
||||
static struct pan_clean_tile
|
||||
pan_get_clean_tile_info(const struct pan_fb_info *fb)
|
||||
struct pan_clean_tile
|
||||
GENX(pan_get_clean_tile_info)(const struct pan_fb_info *fb)
|
||||
{
|
||||
struct pan_clean_tile clean_tile = { 0, };
|
||||
const struct pan_image *img;
|
||||
|
|
@ -1209,7 +1168,7 @@ GENX(pan_emit_fbd)(const struct pan_fb_info *fb, unsigned layer_idx,
|
|||
|
||||
const int crc_rt = GENX(pan_select_crc_rt)(fb, fb->tile_size);
|
||||
const bool has_zs_crc_ext = (fb->zs.view.zs || fb->zs.view.s || crc_rt >= 0);
|
||||
const struct pan_clean_tile clean_tile = pan_get_clean_tile_info(fb);
|
||||
const struct pan_clean_tile clean_tile = GENX(pan_get_clean_tile_info)(fb);
|
||||
|
||||
if (has_zs_crc_ext) {
|
||||
pan_emit_zs_crc_ext(fb, layer_idx, crc_rt, out->zs_crc, clean_tile);
|
||||
|
|
@ -1236,7 +1195,7 @@ GENX(pan_emit_fbd)(const struct pan_fb_info *fb, unsigned layer_idx,
|
|||
|
||||
int crc_rt = GENX(pan_select_crc_rt)(fb, fb->tile_size);
|
||||
bool has_zs_crc_ext = (fb->zs.view.zs || fb->zs.view.s || crc_rt >= 0);
|
||||
struct pan_clean_tile clean_tile = pan_get_clean_tile_info(fb);
|
||||
struct pan_clean_tile clean_tile = GENX(pan_get_clean_tile_info)(fb);
|
||||
|
||||
pan_section_pack(out->fbd, FRAMEBUFFER, PARAMETERS, cfg) {
|
||||
#if PAN_ARCH >= 6
|
||||
|
|
|
|||
|
|
@ -181,6 +181,26 @@ pan_clean_tile_write_any_set(struct pan_clean_tile clean_tile)
|
|||
return clean_tile.write_rt_mask || clean_tile.write_zs;
|
||||
}
|
||||
|
||||
static unsigned
|
||||
pan_zsbuf_bytes_per_pixel(const struct pan_fb_info *fb)
|
||||
{
|
||||
unsigned samples = fb->nr_samples;
|
||||
|
||||
const struct pan_image_view *zs_view = fb->zs.view.zs;
|
||||
if (zs_view)
|
||||
samples = zs_view->nr_samples;
|
||||
|
||||
const struct pan_image_view *s_view = fb->zs.view.s;
|
||||
if (s_view)
|
||||
samples = MAX2(samples, s_view->nr_samples);
|
||||
|
||||
/* Depth is always stored in a 32-bit float. Stencil requires depth to
|
||||
* be allocated, but doesn't have it's own budget; it's tied to the
|
||||
* depth buffer.
|
||||
*/
|
||||
return sizeof(float) * samples;
|
||||
}
|
||||
|
||||
static inline unsigned
|
||||
pan_wls_instances(const struct pan_compute_dim *dim)
|
||||
{
|
||||
|
|
@ -286,11 +306,35 @@ pan_effective_tile_block_size(unsigned tile_size)
|
|||
return (struct pan_image_block_size){w, h};
|
||||
}
|
||||
|
||||
#if PAN_ARCH >= 6
|
||||
/* All GPUs starting from Bifrost are affected by issue TSIX-2033:
|
||||
*
|
||||
* Forcing clean_tile_writes breaks INTERSECT readbacks
|
||||
*
|
||||
* To workaround, use the pre-frame shader mode ALWAYS instead of INTERSECT if
|
||||
* clean_tile_write_enable is set on either one of the color, depth or stencil
|
||||
* buffers. Since INTERSECT is a hint that the hardware may ignore, this
|
||||
* cannot affect correctness, only performance. */
|
||||
|
||||
static enum mali_pre_post_frame_shader_mode
|
||||
pan_fix_frame_shader_mode(enum mali_pre_post_frame_shader_mode mode,
|
||||
bool force_clean_tile)
|
||||
{
|
||||
if (force_clean_tile && mode == MALI_PRE_POST_FRAME_SHADER_MODE_INTERSECT)
|
||||
return MALI_PRE_POST_FRAME_SHADER_MODE_ALWAYS;
|
||||
else
|
||||
return mode;
|
||||
}
|
||||
#endif
|
||||
|
||||
void GENX(pan_select_tile_size)(struct pan_fb_info *fb);
|
||||
|
||||
bool GENX(pan_force_clean_write_on)(const struct pan_image *image,
|
||||
unsigned fb_tile_size_px);
|
||||
|
||||
struct pan_clean_tile
|
||||
GENX(pan_get_clean_tile_info)(const struct pan_fb_info *fb);
|
||||
|
||||
void GENX(pan_emit_tls)(const struct pan_tls_info *info,
|
||||
struct mali_local_storage_packed *out);
|
||||
|
||||
|
|
|
|||
|
|
@ -639,25 +639,6 @@ pan_target_has_clear(const struct pan_fb_load_target *target)
|
|||
bool GENX(pan_fb_resolve_shader_key_fill)(struct pan_fb_shader_key *key,
|
||||
const struct pan_fb_layout *fb,
|
||||
const struct pan_fb_resolve *resolve);
|
||||
|
||||
/* All GPUs starting from Bifrost are affected by issue TSIX-2033:
|
||||
*
|
||||
* Forcing clean_tile_writes breaks INTERSECT readbacks
|
||||
*
|
||||
* To workaround, use the pre-frame shader mode ALWAYS instead of INTERSECT if
|
||||
* clean_tile_write_enable is set on either one of the color, depth or stencil
|
||||
* buffers. Since INTERSECT is a hint that the hardware may ignore, this
|
||||
* cannot affect correctness, only performance. */
|
||||
|
||||
static inline enum mali_pre_post_frame_shader_mode
|
||||
pan_fix_frame_shader_mode(enum mali_pre_post_frame_shader_mode mode,
|
||||
bool force_clean_tile)
|
||||
{
|
||||
if (force_clean_tile && mode == MALI_PRE_POST_FRAME_SHADER_MODE_INTERSECT)
|
||||
return MALI_PRE_POST_FRAME_SHADER_MODE_ALWAYS;
|
||||
else
|
||||
return mode;
|
||||
}
|
||||
#endif /* PAN_ARCH >= 6 */
|
||||
|
||||
struct nir_shader *
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue