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intel/compiler: Add and use helpers for working with KSP indices
The pixel shader dispatch table is kind-of a confusing mess. This adds some helpers for dealing with it and for easily extracting the correct data from wm_prog_data. Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Jason Ekstrand
parent
85750348bc
commit
9d78abbef8
5 changed files with 186 additions and 58 deletions
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@ -763,17 +763,22 @@ blorp_emit_ps_config(struct blorp_batch *batch,
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}
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if (prog_data) {
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ps.DispatchGRFStartRegisterForConstantSetupData0 =
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prog_data->base.dispatch_grf_start_reg;
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ps.DispatchGRFStartRegisterForConstantSetupData2 =
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prog_data->dispatch_grf_start_reg_2;
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ps._8PixelDispatchEnable = prog_data->dispatch_8;
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ps._16PixelDispatchEnable = prog_data->dispatch_16;
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ps.KernelStartPointer0 = params->wm_prog_kernel;
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ps.KernelStartPointer2 =
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params->wm_prog_kernel + prog_data->prog_offset_2;
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ps.DispatchGRFStartRegisterForConstantSetupData0 =
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brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 0);
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ps.DispatchGRFStartRegisterForConstantSetupData1 =
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brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 1);
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ps.DispatchGRFStartRegisterForConstantSetupData2 =
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brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 2);
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ps.KernelStartPointer0 = params->wm_prog_kernel +
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brw_wm_prog_data_prog_offset(prog_data, ps, 0);
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ps.KernelStartPointer1 = params->wm_prog_kernel +
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brw_wm_prog_data_prog_offset(prog_data, ps, 1);
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ps.KernelStartPointer2 = params->wm_prog_kernel +
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brw_wm_prog_data_prog_offset(prog_data, ps, 2);
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}
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/* 3DSTATE_PS expects the number of threads per PSD, which is always 64
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@ -867,18 +872,23 @@ blorp_emit_ps_config(struct blorp_batch *batch,
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#endif
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if (prog_data) {
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ps.DispatchGRFStartRegisterForConstantSetupData0 =
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prog_data->base.dispatch_grf_start_reg;
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ps.DispatchGRFStartRegisterForConstantSetupData2 =
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prog_data->dispatch_grf_start_reg_2;
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ps.KernelStartPointer0 = params->wm_prog_kernel;
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ps.KernelStartPointer2 =
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params->wm_prog_kernel + prog_data->prog_offset_2;
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ps._8PixelDispatchEnable = prog_data->dispatch_8;
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ps._16PixelDispatchEnable = prog_data->dispatch_16;
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ps.DispatchGRFStartRegisterForConstantSetupData0 =
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brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 0);
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ps.DispatchGRFStartRegisterForConstantSetupData1 =
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brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 1);
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ps.DispatchGRFStartRegisterForConstantSetupData2 =
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brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 2);
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ps.KernelStartPointer0 = params->wm_prog_kernel +
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brw_wm_prog_data_prog_offset(prog_data, ps, 0);
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ps.KernelStartPointer1 = params->wm_prog_kernel +
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brw_wm_prog_data_prog_offset(prog_data, ps, 1);
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ps.KernelStartPointer2 = params->wm_prog_kernel +
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brw_wm_prog_data_prog_offset(prog_data, ps, 2);
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ps.AttributeEnable = prog_data->num_varying_inputs > 0;
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} else {
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/* Gen7 hardware gets angry if we don't enable at least one dispatch
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@ -929,18 +939,23 @@ blorp_emit_ps_config(struct blorp_batch *batch,
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if (prog_data) {
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wm.ThreadDispatchEnable = true;
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wm.DispatchGRFStartRegisterForConstantSetupData0 =
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prog_data->base.dispatch_grf_start_reg;
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wm.DispatchGRFStartRegisterForConstantSetupData2 =
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prog_data->dispatch_grf_start_reg_2;
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wm.KernelStartPointer0 = params->wm_prog_kernel;
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wm.KernelStartPointer2 =
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params->wm_prog_kernel + prog_data->prog_offset_2;
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wm._8PixelDispatchEnable = prog_data->dispatch_8;
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wm._16PixelDispatchEnable = prog_data->dispatch_16;
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wm.DispatchGRFStartRegisterForConstantSetupData0 =
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brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm, 0);
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wm.DispatchGRFStartRegisterForConstantSetupData1 =
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brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm, 1);
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wm.DispatchGRFStartRegisterForConstantSetupData2 =
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brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm, 2);
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wm.KernelStartPointer0 = params->wm_prog_kernel +
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brw_wm_prog_data_prog_offset(prog_data, wm, 0);
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wm.KernelStartPointer1 = params->wm_prog_kernel +
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brw_wm_prog_data_prog_offset(prog_data, wm, 1);
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wm.KernelStartPointer2 = params->wm_prog_kernel +
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brw_wm_prog_data_prog_offset(prog_data, wm, 2);
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wm.NumberofSFOutputAttributes = prog_data->num_varying_inputs;
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}
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@ -745,6 +745,91 @@ struct brw_wm_prog_data {
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int urb_setup[VARYING_SLOT_MAX];
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};
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/** Returns the SIMD width corresponding to a given KSP index
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*
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* The "Variable Pixel Dispatch" table in the PRM (which can be found, for
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* example in Vol. 7 of the SKL PRM) has a mapping from dispatch widths to
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* kernel start pointer (KSP) indices that is based on what dispatch widths
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* are enabled. This function provides, effectively, the reverse mapping.
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*
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* If the given KSP is valid with respect to the SIMD8/16/32 enables, a SIMD
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* width of 8, 16, or 32 is returned. If the KSP is invalid, 0 is returned.
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*/
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static inline unsigned
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brw_fs_simd_width_for_ksp(unsigned ksp_idx, bool simd8_enabled,
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bool simd16_enabled, bool simd32_enabled)
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{
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/* This function strictly ignores contiguous dispatch */
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switch (ksp_idx) {
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case 0:
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return simd8_enabled ? 8 :
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(simd16_enabled && !simd32_enabled) ? 16 :
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(simd32_enabled && !simd16_enabled) ? 32 : 0;
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case 1:
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return (simd32_enabled && (simd16_enabled || simd8_enabled)) ? 32 : 0;
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case 2:
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return (simd16_enabled && (simd32_enabled || simd8_enabled)) ? 16 : 0;
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default:
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unreachable("Invalid KSP index");
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}
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}
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#define brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx) \
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brw_fs_simd_width_for_ksp((ksp_idx), (wm_state)._8PixelDispatchEnable, \
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(wm_state)._16PixelDispatchEnable, \
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(wm_state)._32PixelDispatchEnable)
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#define brw_wm_state_has_ksp(wm_state, ksp_idx) \
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(brw_wm_state_simd_width_for_ksp((wm_state), (ksp_idx)) != 0)
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static inline uint32_t
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_brw_wm_prog_data_prog_offset(const struct brw_wm_prog_data *prog_data,
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unsigned ksp_idx)
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{
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switch (ksp_idx) {
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case 0: return 0;
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case 1: return 0;
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case 2: return prog_data->prog_offset_2;
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default:
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unreachable("Invalid KSP index");
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}
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}
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#define brw_wm_prog_data_prog_offset(prog_data, wm_state, ksp_idx) \
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_brw_wm_prog_data_prog_offset(prog_data, ksp_idx)
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static inline uint8_t
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_brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data *prog_data,
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unsigned ksp_idx)
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{
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switch (ksp_idx) {
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case 0: return prog_data->base.dispatch_grf_start_reg;
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case 1: return 0;
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case 2: return prog_data->dispatch_grf_start_reg_2;
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default:
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unreachable("Invalid KSP index");
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}
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}
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#define brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm_state, ksp_idx) \
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_brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ksp_idx)
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static inline uint8_t
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_brw_wm_prog_data_reg_blocks(const struct brw_wm_prog_data *prog_data,
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unsigned ksp_idx)
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{
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switch (ksp_idx) {
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case 0: return prog_data->reg_blocks_0;
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case 1: return 0;
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case 2: return prog_data->reg_blocks_2;
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default:
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unreachable("Invalid KSP index");
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}
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}
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#define brw_wm_prog_data_reg_blocks(prog_data, wm_state, ksp_idx) \
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_brw_wm_prog_data_reg_blocks(prog_data, ksp_idx)
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struct brw_push_const_block {
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unsigned dwords; /* Dword count, not reg aligned */
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unsigned regs;
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@ -1488,14 +1488,17 @@ emit_3dstate_ps(struct anv_pipeline *pipeline,
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#endif
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) {
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ps.KernelStartPointer0 = fs_bin->kernel.offset;
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ps.KernelStartPointer1 = 0;
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ps.KernelStartPointer2 = fs_bin->kernel.offset +
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wm_prog_data->prog_offset_2;
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ps._8PixelDispatchEnable = wm_prog_data->dispatch_8;
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ps._16PixelDispatchEnable = wm_prog_data->dispatch_16;
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ps._32PixelDispatchEnable = false;
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ps.KernelStartPointer0 = fs_bin->kernel.offset +
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brw_wm_prog_data_prog_offset(wm_prog_data, ps, 0);
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ps.KernelStartPointer1 = fs_bin->kernel.offset +
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brw_wm_prog_data_prog_offset(wm_prog_data, ps, 1);
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ps.KernelStartPointer2 = fs_bin->kernel.offset +
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brw_wm_prog_data_prog_offset(wm_prog_data, ps, 2);
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ps.SingleProgramFlow = false;
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ps.VectorMaskEnable = true;
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ps.SamplerCount = get_sampler_count(fs_bin);
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@ -1526,10 +1529,11 @@ emit_3dstate_ps(struct anv_pipeline *pipeline,
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#endif
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ps.DispatchGRFStartRegisterForConstantSetupData0 =
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wm_prog_data->base.dispatch_grf_start_reg;
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ps.DispatchGRFStartRegisterForConstantSetupData1 = 0;
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brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 0);
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ps.DispatchGRFStartRegisterForConstantSetupData1 =
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brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 1);
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ps.DispatchGRFStartRegisterForConstantSetupData2 =
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wm_prog_data->dispatch_grf_start_reg_2;
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brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 2);
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ps.PerThreadScratchSpace = get_scratch_space(fs_bin);
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ps.ScratchSpaceBasePointer =
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@ -136,13 +136,17 @@ blorp_emit_wm_state(struct blorp_batch *batch,
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#if GEN_GEN == 4
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wm.KernelStartPointer0 =
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instruction_state_address(batch, params->wm_prog_kernel);
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wm.GRFRegisterCount0 = prog_data->reg_blocks_0;
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wm.GRFRegisterCount0 = brw_wm_prog_data_reg_blocks(prog_data, wm, 0);
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#else
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wm.KernelStartPointer0 = params->wm_prog_kernel;
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wm.GRFRegisterCount0 = prog_data->reg_blocks_0;
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wm.KernelStartPointer2 =
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params->wm_prog_kernel + prog_data->prog_offset_2;
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wm.GRFRegisterCount2 = prog_data->reg_blocks_2;
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wm.KernelStartPointer0 = params->wm_prog_kernel +
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brw_wm_prog_data_prog_offset(prog_data, wm, 0);
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wm.KernelStartPointer1 = params->wm_prog_kernel +
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brw_wm_prog_data_prog_offset(prog_data, wm, 1);
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wm.KernelStartPointer2 = params->wm_prog_kernel +
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brw_wm_prog_data_prog_offset(prog_data, wm, 2);
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wm.GRFRegisterCount0 = brw_wm_prog_data_reg_blocks(prog_data, wm, 0);
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wm.GRFRegisterCount1 = brw_wm_prog_data_reg_blocks(prog_data, wm, 1);
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wm.GRFRegisterCount2 = brw_wm_prog_data_reg_blocks(prog_data, wm, 2);
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#endif
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}
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@ -1899,43 +1899,57 @@ genX(upload_wm)(struct brw_context *brw)
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#if GEN_GEN == 4
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/* On gen4, we only have one shader kernel */
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if (wm_prog_data->dispatch_8 || wm_prog_data->dispatch_16) {
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if (brw_wm_state_has_ksp(wm, 0)) {
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assert(brw_wm_prog_data_prog_offset(wm_prog_data, wm, 0) == 0);
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wm.KernelStartPointer0 = KSP(brw, stage_state->prog_offset);
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wm.GRFRegisterCount0 = wm_prog_data->reg_blocks_0;
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wm.GRFRegisterCount0 = brw_wm_prog_data_reg_blocks(wm_prog_data, wm, 0);
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wm.DispatchGRFStartRegisterForConstantSetupData0 =
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wm_prog_data->base.dispatch_grf_start_reg;
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brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, wm, 0);
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}
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#elif GEN_GEN == 5
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/* On gen5, we have multiple shader kernels but only one GRF start
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* register for all kernels
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*/
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wm.KernelStartPointer0 = stage_state->prog_offset;
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wm.KernelStartPointer0 = stage_state->prog_offset +
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brw_wm_prog_data_prog_offset(wm_prog_data, wm, 0);
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wm.KernelStartPointer1 = stage_state->prog_offset +
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brw_wm_prog_data_prog_offset(wm_prog_data, wm, 1);
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wm.KernelStartPointer2 = stage_state->prog_offset +
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wm_prog_data->prog_offset_2;
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brw_wm_prog_data_prog_offset(wm_prog_data, wm, 2);
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wm.GRFRegisterCount0 = wm_prog_data->reg_blocks_0;
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wm.GRFRegisterCount2 = wm_prog_data->reg_blocks_2;
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wm.GRFRegisterCount0 = brw_wm_prog_data_reg_blocks(wm_prog_data, wm, 0);
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wm.GRFRegisterCount1 = brw_wm_prog_data_reg_blocks(wm_prog_data, wm, 1);
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wm.GRFRegisterCount2 = brw_wm_prog_data_reg_blocks(wm_prog_data, wm, 2);
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wm.DispatchGRFStartRegisterForConstantSetupData0 =
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wm_prog_data->base.dispatch_grf_start_reg;
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/* Dispatch GRF Start should be the same for all shaders on gen5 */
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if (wm_prog_data->dispatch_8 && wm_prog_data->dispatch_16) {
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if (brw_wm_state_has_ksp(wm, 1)) {
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assert(wm_prog_data->base.dispatch_grf_start_reg ==
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wm_prog_data->dispatch_grf_start_reg_2);
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brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, wm, 1));
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}
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if (brw_wm_state_has_ksp(wm, 2)) {
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assert(wm_prog_data->base.dispatch_grf_start_reg ==
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brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, wm, 2));
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}
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#elif GEN_GEN == 6
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/* On gen5, we have multiple shader kernels and we no longer specify a
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* register count for each one.
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*/
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wm.KernelStartPointer0 = stage_state->prog_offset;
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wm.KernelStartPointer0 = stage_state->prog_offset +
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brw_wm_prog_data_prog_offset(wm_prog_data, wm, 0);
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wm.KernelStartPointer1 = stage_state->prog_offset +
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brw_wm_prog_data_prog_offset(wm_prog_data, wm, 1);
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wm.KernelStartPointer2 = stage_state->prog_offset +
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wm_prog_data->prog_offset_2;
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brw_wm_prog_data_prog_offset(wm_prog_data, wm, 2);
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wm.DispatchGRFStartRegisterForConstantSetupData0 =
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wm_prog_data->base.dispatch_grf_start_reg;
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brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, wm, 0);
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wm.DispatchGRFStartRegisterForConstantSetupData1 =
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brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, wm, 1);
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wm.DispatchGRFStartRegisterForConstantSetupData2 =
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wm_prog_data->dispatch_grf_start_reg_2;
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brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, wm, 2);
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#endif
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#if GEN_GEN <= 5
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@ -4015,14 +4029,20 @@ genX(upload_ps)(struct brw_context *brw)
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ps._8PixelDispatchEnable = prog_data->dispatch_8;
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ps._16PixelDispatchEnable = prog_data->dispatch_16;
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ps.DispatchGRFStartRegisterForConstantSetupData0 =
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prog_data->base.dispatch_grf_start_reg;
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ps.DispatchGRFStartRegisterForConstantSetupData2 =
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prog_data->dispatch_grf_start_reg_2;
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ps.KernelStartPointer0 = stage_state->prog_offset;
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ps.DispatchGRFStartRegisterForConstantSetupData0 =
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brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 0);
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ps.DispatchGRFStartRegisterForConstantSetupData1 =
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brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 1);
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ps.DispatchGRFStartRegisterForConstantSetupData2 =
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brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 2);
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ps.KernelStartPointer0 = stage_state->prog_offset +
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brw_wm_prog_data_prog_offset(prog_data, ps, 0);
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ps.KernelStartPointer1 = stage_state->prog_offset +
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brw_wm_prog_data_prog_offset(prog_data, ps, 1);
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ps.KernelStartPointer2 = stage_state->prog_offset +
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prog_data->prog_offset_2;
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brw_wm_prog_data_prog_offset(prog_data, ps, 2);
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if (prog_data->base.total_scratch) {
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ps.ScratchSpaceBasePointer =
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