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radeonsi/vcn: Add radeon_enc_av1_picture_type

Browse source 
Reviewed-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33845>
This commit is contained in:
David Rosca 2025-03-03 13:26:35 +01:00 • committed by Marge Bot
parent d92781508b
commit 9d020826ca
5 changed files with 26 additions and 74 deletions
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15
src/gallium/drivers/radeonsi/radeon_vcn_enc.c
View file

@ -2123,6 +2123,21 @@ unsigned int radeon_enc_h2645_picture_type(enum pipe_h2645_enc_picture_type type
}
}
unsigned int radeon_enc_av1_picture_type(enum pipe_av1_enc_frame_type type)
{
switch (type) {
case PIPE_AV1_ENC_FRAME_TYPE_KEY:
case PIPE_AV1_ENC_FRAME_TYPE_INTRA_ONLY:
return RENCODE_PICTURE_TYPE_I;
case PIPE_AV1_ENC_FRAME_TYPE_INTER:
case PIPE_AV1_ENC_FRAME_TYPE_SWITCH:
return RENCODE_PICTURE_TYPE_P;
default:
assert(false);
return 0;
}
}
/* dummy function for re-using the same pipeline */
void radeon_enc_dummy(struct radeon_encoder *enc) {}

2
src/gallium/drivers/radeonsi/radeon_vcn_enc.h
View file

@ -345,6 +345,8 @@ unsigned int radeon_enc_av1_tile_log2(unsigned int blk_size, unsigned int max);
unsigned int radeon_enc_h2645_picture_type(enum pipe_h2645_enc_picture_type type);
unsigned int radeon_enc_av1_picture_type(enum pipe_av1_enc_frame_type type);
bool radeon_enc_is_av1_uniform_tile (uint32_t nb_sb, uint32_t nb_tiles,
uint32_t min_nb_sb, struct tile_1d_layout *p);

19
src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c
View file

@ -1030,27 +1030,10 @@ static void radeon_enc_rc_per_pic_ex(struct radeon_encoder *enc)
static void radeon_enc_encode_params(struct radeon_encoder *enc)
{
switch (enc->enc_pic.picture_type) {
case PIPE_H2645_ENC_PICTURE_TYPE_I:
case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
break;
case PIPE_H2645_ENC_PICTURE_TYPE_P:
enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
break;
case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
break;
case PIPE_H2645_ENC_PICTURE_TYPE_B:
enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
break;
default:
enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
}
if (enc->luma->meta_offset)
RADEON_ENC_ERR("DCC surfaces not supported.\n");
enc->enc_pic.enc_params.pic_type = radeon_enc_h2645_picture_type(enc->enc_pic.picture_type);
enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma ?
enc->chroma->u.gfx9.surf_pitch : enc->luma->u.gfx9.surf_pitch;

16
src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c
View file

@ -620,24 +620,10 @@ static void radeon_enc_obu_instruction(struct radeon_encoder *enc)
/* av1 encode params */
static void radeon_enc_av1_encode_params(struct radeon_encoder *enc)
{
switch (enc->enc_pic.frame_type) {
case PIPE_AV1_ENC_FRAME_TYPE_KEY:
enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
break;
case PIPE_AV1_ENC_FRAME_TYPE_INTRA_ONLY:
enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
break;
case PIPE_AV1_ENC_FRAME_TYPE_INTER:
case PIPE_AV1_ENC_FRAME_TYPE_SWITCH:
enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
break;
default:
assert(0); /* never come to this condition */
}
if (enc->luma->meta_offset)
RADEON_ENC_ERR("DCC surfaces not supported.\n");
enc->enc_pic.enc_params.pic_type = radeon_enc_av1_picture_type(enc->enc_pic.frame_type);
enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma ?
enc->chroma->u.gfx9.surf_pitch : enc->luma->u.gfx9.surf_pitch;

48
src/gallium/drivers/radeonsi/radeon_vcn_enc_5_0.c
View file

@ -50,50 +50,16 @@ static void radeon_enc_spec_misc(struct radeon_encoder *enc)
static void radeon_enc_encode_params(struct radeon_encoder *enc)
{
bool is_av1 = u_reduce_video_profile(enc->base.profile)
== PIPE_VIDEO_FORMAT_AV1;
if ( !is_av1 ) {
switch (enc->enc_pic.picture_type) {
case PIPE_H2645_ENC_PICTURE_TYPE_I:
case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
break;
case PIPE_H2645_ENC_PICTURE_TYPE_P:
enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
break;
case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
break;
case PIPE_H2645_ENC_PICTURE_TYPE_B:
enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
break;
default:
enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
}
} else {
switch (enc->enc_pic.frame_type) {
case PIPE_AV1_ENC_FRAME_TYPE_KEY:
enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
break;
case PIPE_AV1_ENC_FRAME_TYPE_INTRA_ONLY:
enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
break;
case PIPE_AV1_ENC_FRAME_TYPE_INTER:
case PIPE_AV1_ENC_FRAME_TYPE_SWITCH:
if (enc->enc_pic.av1.compound)
enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
else
enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
break;
default:
assert(0); /* never come to this condition */
}
}
if (enc->luma->meta_offset)
RADEON_ENC_ERR("DCC surfaces not supported.\n");
if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_AV1) {
enc->enc_pic.enc_params.pic_type = radeon_enc_av1_picture_type(enc->enc_pic.frame_type);
if (enc->enc_pic.enc_params.pic_type == RENCODE_PICTURE_TYPE_P && enc->enc_pic.av1.compound)
enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
} else {
enc->enc_pic.enc_params.pic_type = radeon_enc_h2645_picture_type(enc->enc_pic.picture_type);
}
enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma ?
enc->chroma->u.gfx9.surf_pitch : enc->luma->u.gfx9.surf_pitch;