diff --git a/src/amd/common/ac_cmdbuf.c b/src/amd/common/ac_cmdbuf.c
index 27fb647016f..8f2f69c92c8 100644
--- a/src/amd/common/ac_cmdbuf.c
+++ b/src/amd/common/ac_cmdbuf.c
@@ -986,7 +986,7 @@ ac_set_tracked_regs_to_clear_state(struct ac_tracked_regs *tracked_regs,
    tracked_regs->reg_value[AC_TRACKED_CB_DCC_CONTROL] = 0;
    tracked_regs->reg_value[AC_TRACKED_CB_COLOR_CONTROL] = 0;
 
-   tracked_regs->reg_value[AC_TRACKED_PA_SC_VRS_OVERRIDE_CNTL] = 0;
+   tracked_regs->reg_value[AC_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL] = 0;
 
    /* Set all cleared context registers to saved. */
    BITSET_SET_COUNT(tracked_regs->reg_saved_mask, 0, AC_NUM_TRACKED_CONTEXT_REGS);
diff --git a/src/amd/common/ac_cmdbuf.h b/src/amd/common/ac_cmdbuf.h
index 77944e55dcb..e5d78e5321c 100644
--- a/src/amd/common/ac_cmdbuf.h
+++ b/src/amd/common/ac_cmdbuf.h
@@ -252,7 +252,9 @@ enum ac_tracked_reg
    AC_TRACKED_SPI_SHADER_GS_MESHLET_EXP_ALLOC, /* GFX11+ */
    AC_TRACKED_SPI_SHADER_GS_MESHLET_CTRL,      /* GFX12+ */
 
-   AC_TRACKED_PA_SC_VRS_OVERRIDE_CNTL,         /* GFX11+ */
+   /* This spot is only for new SH and UCONFIG register enums.
+    * Context register enums should be before AC_NUM_TRACKED_CONTEXT_REGS.
+    */
 
    AC_NUM_ALL_TRACKED_REGS,
 };
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 06fdbecee14..3b60e6e210c 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3860,16 +3860,16 @@ gfx103_emit_vrs_state(struct radv_cmd_buffer *cmd_buffer)
       radeon_begin(cs);
       if (pdev->info.gfx_level >= GFX12) {
          gfx12_begin_context_regs();
-         gfx12_opt_set_context_reg(R_0283D0_PA_SC_VRS_OVERRIDE_CNTL, AC_TRACKED_PA_SC_VRS_OVERRIDE_CNTL,
+         gfx12_opt_set_context_reg(R_0283D0_PA_SC_VRS_OVERRIDE_CNTL, AC_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL,
                                    pa_sc_vrs_override_cntl);
          gfx12_end_context_regs();
       } else if (pdev->info.has_set_context_pairs_packed) {
          gfx11_begin_packed_context_regs();
-         gfx11_opt_set_context_reg(R_0283D0_PA_SC_VRS_OVERRIDE_CNTL, AC_TRACKED_PA_SC_VRS_OVERRIDE_CNTL,
+         gfx11_opt_set_context_reg(R_0283D0_PA_SC_VRS_OVERRIDE_CNTL, AC_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL,
                                    pa_sc_vrs_override_cntl);
          gfx11_end_packed_context_regs();
       } else {
-         radeon_opt_set_context_reg(R_0283D0_PA_SC_VRS_OVERRIDE_CNTL, AC_TRACKED_PA_SC_VRS_OVERRIDE_CNTL,
+         radeon_opt_set_context_reg(R_0283D0_PA_SC_VRS_OVERRIDE_CNTL, AC_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL,
                                     pa_sc_vrs_override_cntl);
       }
       radeon_end();