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radeonsi: handle non-clearable DCC buffers as MSAA resolve dst

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This is reproducible on Stoney, but other chips may be affected too.

Cc 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Marek Olšák 2018-06-20 18:15:36 -05:00
parent 587e712eda
commit 9c21002f6e
2 changed files with 6 additions and 1 deletions
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5
src/gallium/drivers/radeonsi/si_blit.c
View file

@ -1161,6 +1161,11 @@ static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
info->dst.resource->last_level != 0)
goto resolve_to_temp;
/* This can happen with mipmapping. */
if (sctx->chip_class == VI &&
!dst->surface.u.legacy.level[info->dst.level].dcc_fast_clear_size)
goto resolve_to_temp;
vi_dcc_clear_level(sctx, dst, info->dst.level,
0xFFFFFFFF);
dst->dirty_level_mask &= ~(1 << info->dst.level);

2
src/gallium/drivers/radeonsi/si_clear.c
View file

@ -479,7 +479,7 @@ static void si_do_fast_color_clear(struct si_context *sctx,
if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
continue;
/* This can only occur with MSAA. */
/* This can happen with mipmapping or MSAA. */
if (sctx->chip_class == VI &&
!tex->surface.u.legacy.level[level].dcc_fast_clear_size)
continue;