From 9b5ba0612260c21b016cbc704c9a1c70d17910fd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Date: Mon, 1 Jul 2024 07:38:18 -0700 Subject: [PATCH] intel/perf: Do not add INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_PEC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MI_REPORT_PERF_COUNT reports all 64 PEC counters, so there is no need to read individual registers. Also the individual registers reads privileged and UMDs can't access it, causing it to always read as always zero and overwritting valid data read with MI_REPORT_PERF_COUNT. Reviewed-by: Lionel Landwerlin Signed-off-by: José Roberto de Souza Part-of: --- src/intel/perf/intel_perf.c | 5 ----- src/intel/perf/intel_perf_regs.h | 3 --- 2 files changed, 8 deletions(-) diff --git a/src/intel/perf/intel_perf.c b/src/intel/perf/intel_perf.c index cb1b6f67423..a50dbd6d06c 100644 --- a/src/intel/perf/intel_perf.c +++ b/src/intel/perf/intel_perf.c @@ -1505,11 +1505,6 @@ intel_perf_init_query_fields(struct intel_perf_config *perf_cfg, add_query_register(perf_cfg, INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_C, GFX12_OAG_PERF_C32(i), 4, i); } - } else if (devinfo->verx10 >= 200) { - for (uint32_t i = 0; i < XE2_N_OAG_PERF_PEC; i++) { - add_query_register(perf_cfg, INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_PEC, - XE2_OAG_PERF_PEC(i), 8, i); - } } } } diff --git a/src/intel/perf/intel_perf_regs.h b/src/intel/perf/intel_perf_regs.h index cb224c74ecd..ae406cb9c2b 100644 --- a/src/intel/perf/intel_perf_regs.h +++ b/src/intel/perf/intel_perf_regs.h @@ -74,9 +74,6 @@ #define GFX125_OAG_PERF_A36 (0xdb20) #define GFX125_OAG_PERF_A37 (0xdb28) -#define XE2_N_OAG_PERF_PEC 64 -#define XE2_OAG_PERF_PEC(idx) (0x14200 + (idx) * 8) - /* Pipeline statistic counters */ #define IA_VERTICES_COUNT 0x2310 #define IA_PRIMITIVES_COUNT 0x2318