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gallium: rename continue shader-cap

Browse source 
This is no longer TGSI specific, so let's rename it to reflect
reality.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15922>
This commit is contained in:
Erik Faye-Lund 2022-04-13 12:46:55 +02:00 • committed by Marge Bot
parent d275d6c32f
commit 9b545ea691
24 changed files with 28 additions and 28 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
docs/gallium/screen.rst
View file

@ -699,7 +699,7 @@ DCL CONST[3][0] # declare first vector of constbuf 3
MOV OUT[0], CONST[0][3] # copy vector 3 of constbuf 0
* ``PIPE_SHADER_CAP_MAX_TEMPS``: The maximum number of temporary registers.
* ``PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED``: Whether the continue opcode is supported.
* ``PIPE_SHADER_CAP_CONT_SUPPORTED``: Whether continue is supported.
* ``PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR``: Whether indirect addressing
of the input file is supported.
* ``PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR``: Whether indirect addressing

2
src/gallium/auxiliary/gallivm/lp_bld_limits.h
View file

@ -119,7 +119,7 @@ gallivm_get_shader_param(enum pipe_shader_cap param)
return LP_MAX_TGSI_CONST_BUFFERS;
case PIPE_SHADER_CAP_MAX_TEMPS:
return LP_MAX_TGSI_TEMPS;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:

2
src/gallium/auxiliary/tgsi/tgsi_exec.h
View file

@ -452,7 +452,7 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param)
return PIPE_MAX_CONSTANT_BUFFERS;
case PIPE_SHADER_CAP_MAX_TEMPS:
return TGSI_EXEC_NUM_TEMPS;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:

2
src/gallium/drivers/asahi/agx_pipe.c
View file

@ -921,7 +921,7 @@ agx_get_shader_param(struct pipe_screen* pscreen,
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return 16;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:

2
src/gallium/drivers/crocus/crocus_screen.c
View file

@ -484,7 +484,7 @@ crocus_get_shader_param(struct pipe_screen *pscreen,
return devinfo->ver >= 6 ? 16 : 1;
case PIPE_SHADER_CAP_MAX_TEMPS:
return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:

2
src/gallium/drivers/d3d12/d3d12_screen.cpp
View file

@ -492,7 +492,7 @@ d3d12_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 0; /* not implemented */
/* should only get here on unhandled cases */

2
src/gallium/drivers/etnaviv/etnaviv_screen.c
View file

@ -374,7 +374,7 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen,
return 64; /* Max native temporaries. */
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return ubo_enable ? ETNA_MAX_CONST_BUF : 1;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:

2
src/gallium/drivers/freedreno/freedreno_screen.c
View file

@ -635,7 +635,7 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
sizeof(float[4]);
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return is_ir3(screen) ? 16 : 1;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:

2
src/gallium/drivers/i915/i915_screen.c
View file

@ -343,7 +343,7 @@ i915_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
case PIPE_SHADER_CAP_MAX_TEMPS:
/* 16 inter-phase temps, 3 intra-phase temps. i915c reported 16. too. */
return 16;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:

2
src/gallium/drivers/iris/iris_screen.c
View file

@ -456,7 +456,7 @@ iris_get_shader_param(struct pipe_screen *pscreen,
return 16;
case PIPE_SHADER_CAP_MAX_TEMPS:
return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:

4
src/gallium/drivers/nouveau/nv30/nv30_screen.c
View file

@ -353,7 +353,7 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return 0;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
@ -412,7 +412,7 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen,
return 32;
case PIPE_SHADER_CAP_PREFERRED_IR:
return (NOUVEAU_DEBUG & NOUVEAU_DEBUG_USE_TGSI) ? PIPE_SHADER_IR_TGSI : PIPE_SHADER_IR_NIR;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:

2
src/gallium/drivers/nouveau/nv50/nv50_screen.c
View file

@ -485,7 +485,7 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen,
return 1;
case PIPE_SHADER_CAP_MAX_TEMPS:
return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return 1;

2
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
View file

@ -533,7 +533,7 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
return 1;
case PIPE_SHADER_CAP_MAX_TEMPS:
return NVC0_CAP_MAX_PROGRAM_TEMPS;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return 1;

2
src/gallium/drivers/panfrost/pan_screen.c
View file

@ -382,7 +382,7 @@ panfrost_get_shader_param(struct pipe_screen *screen,
STATIC_ASSERT(PAN_MAX_CONST_BUFFERS < 0x100);
return PAN_MAX_CONST_BUFFERS;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:

4
src/gallium/drivers/r300/r300_screen.c
View file

@ -297,7 +297,7 @@ static int r300_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return r300screen->caps.num_tex_units;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
@ -392,7 +392,7 @@ static int r300_get_shader_param(struct pipe_screen *pscreen,
return 1;
case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:

2
src/gallium/drivers/r600/r600_pipe.c
View file

@ -606,7 +606,7 @@ static int r600_get_shader_param(struct pipe_screen* pscreen,
}
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return R600_MAX_USER_CONST_BUFFERS;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return 1;

2
src/gallium/drivers/radeonsi/si_get.c
View file

@ -450,7 +450,7 @@ static int si_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_typ
(1 << PIPE_SHADER_IR_NIR);
/* Supported boolean features. */
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:

6
src/gallium/drivers/svga/svga_screen.c
View file

@ -514,7 +514,7 @@ vgpu9_get_shader_param(struct pipe_screen *screen,
* does it is better to defer loop unrolling to the gallium frontend.
*/
return 0;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return 0;
@ -582,7 +582,7 @@ vgpu9_get_shader_param(struct pipe_screen *screen,
case PIPE_SHADER_CAP_MAX_TEMPS:
val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
return MIN2(val, SVGA3D_TEMPREG_MAX);
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return 0;
@ -706,7 +706,7 @@ vgpu10_get_shader_param(struct pipe_screen *screen,
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return TRUE; /* XXX verify */
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
case PIPE_SHADER_CAP_SUBROUTINES:
case PIPE_SHADER_CAP_INTEGERS:

2
src/gallium/drivers/svga/svga_tgsi_insn.c
View file

@ -2933,7 +2933,7 @@ svga_emit_instruction(struct svga_shader_emitter *emit,
return emit_scalar_op1( emit, SVGA3DOP_RCP, insn );
case TGSI_OPCODE_CONT:
/* not expected (we return PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED = 0) */
/* not expected (we return PIPE_SHADER_CAP_CONT_SUPPORTED = 0) */
return FALSE;
case TGSI_OPCODE_RET:

2
src/gallium/drivers/v3d/v3d_screen.c
View file

@ -399,7 +399,7 @@ v3d_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
return 16 * 1024 * sizeof(float);
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return 16;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
/* We don't currently support this in the backend, but that is

2
src/gallium/drivers/vc4/vc4_screen.c
View file

@ -280,7 +280,7 @@ vc4_screen_get_shader_param(struct pipe_screen *pscreen,
return 16 * 1024 * sizeof(float);
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return 1;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:

2
src/gallium/drivers/zink/zink_screen.c
View file

@ -1026,7 +1026,7 @@ zink_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
return 0; /* not implemented */
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 1;
}

2
src/gallium/include/pipe/p_defines.h
View file

@ -1081,7 +1081,7 @@ enum pipe_shader_cap
PIPE_SHADER_CAP_MAX_CONST_BUFFERS,
PIPE_SHADER_CAP_MAX_TEMPS,
/* boolean caps */
PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED,
PIPE_SHADER_CAP_CONT_SUPPORTED,
PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR,
PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR,
PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR,

2
src/mesa/state_tracker/st_extensions.c
View file

@ -339,7 +339,7 @@ void st_init_limits(struct pipe_screen *screen,
options->EmitNoCont =
!screen->get_shader_param(screen, sh,
PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED);
PIPE_SHADER_CAP_CONT_SUPPORTED);
options->EmitNoIndirectInput =
!screen->get_shader_param(screen, sh,