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Merge remote-tracking branch 'mesa-public/master' into vulkan

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This commit is contained in:
Jason Ekstrand 2015-08-25 17:12:03 -07:00
commit 9b387b5d3f
247 changed files with 7119 additions and 3907 deletions
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4
Makefile.am
View file

@ -32,7 +32,9 @@ AM_DISTCHECK_CONFIGURE_FLAGS = \
--enable-vdpau \
--enable-xa \
--enable-xvmc \
--with-egl-platforms=x11,wayland,drm
--with-egl-platforms=x11,wayland,drm \
--with-dri-drivers=i915,i965,nouveau,radeon,r200,swrast \
--with-gallium-drivers=i915,ilo,nouveau,r300,r600,radeonsi,freedreno,svga,swrast
ACLOCAL_AMFLAGS = -I m4

2
VERSION
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@ -1 +1 @@
11.0.0-devel
11.1.0-devel

6
configure.ac
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@ -74,7 +74,7 @@ LIBDRM_AMDGPU_REQUIRED=2.4.63
LIBDRM_INTEL_REQUIRED=2.4.61
LIBDRM_NVVIEUX_REQUIRED=2.4.33
LIBDRM_NOUVEAU_REQUIRED=2.4.62
LIBDRM_FREEDRENO_REQUIRED=2.4.57
LIBDRM_FREEDRENO_REQUIRED=2.4.64
DRI2PROTO_REQUIRED=2.6
DRI3PROTO_REQUIRED=1.0
PRESENTPROTO_REQUIRED=1.0
@ -1639,6 +1639,10 @@ if test "x$enable_nine" = xyes; then
if test "x$with_gallium_drivers" = xswrast; then
AC_MSG_ERROR([nine requires at least one non-swrast gallium driver])
fi
if test $GCC_VERSION_MAJOR -lt 4 -o $GCC_VERSION_MAJOR -eq 4 -a $GCC_VERSION_MINOR -lt 6; then
AC_MSG_ERROR([gcc >= 4.6 is required to build nine])
fi
if test "x$enable_dri3" = xno; then
AC_MSG_WARN([using nine together with wine requires DRI3 enabled system])
fi

6
docs/GL3.txt
View file

@ -163,7 +163,7 @@ GL 4.3, GLSL 4.30:
GL_ARB_multi_draw_indirect DONE (i965, nvc0, r600, radeonsi, llvmpipe, softpipe)
GL_ARB_program_interface_query DONE (all drivers)
GL_ARB_robust_buffer_access_behavior not started
GL_ARB_shader_image_size in progress (Martin Peres)
GL_ARB_shader_image_size DONE (i965)
GL_ARB_shader_storage_buffer_object in progress (Iago Toral, Samuel Iglesias)
GL_ARB_stencil_texturing DONE (i965/gen8+, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe)
GL_ARB_texture_buffer_range DONE (nv50, nvc0, i965, r600, radeonsi, llvmpipe)
@ -210,8 +210,8 @@ GLES3.1, GLSL ES 3.1
GL_ARB_framebuffer_no_attachments DONE (i965)
GL_ARB_program_interface_query DONE (all drivers)
GL_ARB_shader_atomic_counters DONE (i965)
GL_ARB_shader_image_load_store in progress (curro)
GL_ARB_shader_image_size in progress (Martin Peres)
GL_ARB_shader_image_load_store DONE (i965)
GL_ARB_shader_image_size DONE (i965)
GL_ARB_shader_storage_buffer_object in progress (Iago Toral, Samuel Iglesias)
GL_ARB_shading_language_packing DONE (all drivers)
GL_ARB_separate_shader_objects DONE (all drivers)

6
docs/index.html
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@ -16,6 +16,12 @@
<h1>News</h1>
<h2>August 22 2015</h2>
<p>
<a href="relnotes/10.6.5.html">Mesa 10.6.5</a> is released.
This is a bug-fix release.
</p>
<h2>August 11 2015</h2>
<p>
<a href="relnotes/10.6.4.html">Mesa 10.6.4</a> is released.

1
docs/relnotes.html
View file

@ -21,6 +21,7 @@ The release notes summarize what's new or changed in each Mesa release.
</p>
<ul>
<li><a href="relnotes/10.6.5.html">10.6.5 release notes</a>
<li><a href="relnotes/10.6.4.html">10.6.4 release notes</a>
<li><a href="relnotes/10.6.3.html">10.6.3 release notes</a>
<li><a href="relnotes/10.6.2.html">10.6.2 release notes</a>

124
docs/relnotes/10.6.5.html Normal file
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@ -0,0 +1,124 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 10.6.5 Release Notes / August 22, 2015</h1>
<p>
Mesa 10.6.5 is a bug fix release which fixes bugs found since the 10.6.4 release.
</p>
<p>
Mesa 10.6.5 implements the OpenGL 3.3 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 3.3. OpenGL
3.3 is <strong>only</strong> available if requested at context creation
because compatibility contexts are not supported.
</p>
<h2>SHA256 checksums</h2>
<pre>
afe290fc7af75a25df5ee52396a9f09e5dba85fb3e159304bdda265b8564b0d4 mesa-10.6.5.tar.gz
fb6fac3c85bcfa9d06b8dd439169f23f0c0924a88e44362e738b99b1feff762f mesa-10.6.5.tar.xz
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<p>This list is likely incomplete.</p>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=85252">Bug 85252</a> - Segfault in compiler while processing ternary operator with void arguments</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=91570">Bug 91570</a> - Upgrading mesa to 10.6 causes segfault in OpenGL applications with GeForce4 MX 440 / AGP 8X</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=91610">Bug 91610</a> - [BSW] GPU hang for spec.shaders.point-vertex-id gl_instanceid divisor</li>
</ul>
<h2>Changes</h2>
<p>Adam Jackson (1):</p>
<ul>
<li>glx: Fix __glXWireToEvent for BufferSwapComplete</li>
</ul>
<p>Alex Deucher (2):</p>
<ul>
<li>radeonsi: add new OLAND pci id</li>
<li>radeonsi: properly set the raster_config for KV</li>
</ul>
<p>Emil Velikov (4):</p>
<ul>
<li>docs: add sha256 checksums for 10.6.4</li>
<li>vc4: add missing nir include, to fix the build</li>
<li>Revert "radeonsi: properly set the raster_config for KV"</li>
<li>Update version to 10.6.5</li>
</ul>
<p>Frank Binns (1):</p>
<ul>
<li>egl/x11: don't abort when creating a DRI2 drawable fails</li>
</ul>
<p>Ilia Mirkin (3):</p>
<ul>
<li>nouveau: no need to do tnl wakeup, state updates are always hooked up</li>
<li>gm107/ir: indirect handle goes first on maxwell also</li>
<li>nv50,nvc0: take level into account when doing eng2d multi-layer blits</li>
</ul>
<p>Jason Ekstrand (4):</p>
<ul>
<li>meta/copy_image: Stash off the scissor</li>
<li>mesa/formats: Only do byteswapping for packed formats</li>
<li>mesa/formats: Fix swizzle flipping for big-endian targets</li>
<li>mesa/formats: Don't flip channels of null array formats</li>
</ul>
<p>Marek Olšák (3):</p>
<ul>
<li>radeonsi: fix polygon offset scale</li>
<li>r600g: fix polygon offset scale</li>
<li>r600g: allow setting geometry shader sampler states</li>
</ul>
<p>Neil Roberts (1):</p>
<ul>
<li>i965/bdw: Fix setting the instancing state for the SGVS element</li>
</ul>
<p>Oded Gabbay (2):</p>
<ul>
<li>mesa: clear existing swizzle info before bitwise-OR</li>
<li>mesa/formats: don't byteswap when building array formats</li>
</ul>
<p>Renaud Gaubert (1):</p>
<ul>
<li>glsl: avoid compiler's segfault when processing operators with void arguments</li>
</ul>
</div>
</body>
</html>

7
docs/relnotes/11.0.0.html
View file

@ -46,9 +46,12 @@ Note: some of the new features are only available with certain drivers.
<ul>
<li>New hardware support for AMD GCN 1.2 GPUs: Tonga, Iceland, Carrizo, Fiji</li>
<li>OpenGL 4.1 on radeonsi, nvc0</li>
<li>OpenGL ES 3.0 on freedreno (a3xx, a4xx)
<li>GL_AMD_vertex_shader_viewport_index on radeonsi</li>
<li>GL_ARB_conditional_render_inverted on r600, radeonsi</li>
<li>GL_ARB_depth_buffer_float on a4xx</li>
<li>GL_ARB_derivative_control on radeonsi</li>
<li>GL_ARB_draw_buffers, GL_ARB_draw_buffers_blend on a4xx</li>
<li>GL_ARB_fragment_layer_viewport on radeonsi</li>
<li>GL_ARB_framebuffer_no_attachments on i965</li>
<li>GL_ARB_get_texture_sub_image for all drivers</li>
@ -56,12 +59,15 @@ Note: some of the new features are only available with certain drivers.
<li>GL_ARB_gpu_shader_fp64 on llvmpipe, radeonsi</li>
<li>GL_ARB_shader_image_load_store on i965</li>
<li>GL_ARB_shader_precision on radeonsi, nvc0</li>
<li>GL_ARB_shader_image_size on i965</li>
<li>GL_ARB_shader_stencil_export on llvmpipe</li>
<li>GL_ARB_shader_subroutine on core profile all drivers</li>
<li>GL_ARB_tessellation_shader on nvc0, radeonsi</li>
<li>GL_ARB_transform_feedback2, GL_ARB_transform_feedback_instanced, GL_EXT_transform_feedback on a3xx, a4xx</li>
<li>GL_ARB_vertex_attrib_64bit on llvmpipe, radeonsi</li>
<li>GL_ARB_viewport_array on radeonsi</li>
<li>GL_EXT_depth_bounds_test on radeonsi, nv30, nv50, nvc0</li>
<li>GL_EXT_texture_compression_s3tc on freedreno (a3xx)</li>
<li>GL_NV_read_depth (GLES) on all drivers</li>
<li>GL_NV_read_depth_stencil (GLES) on all drivers</li>
<li>GL_NV_read_stencil (GLES) on all drivers</li>
@ -69,6 +75,7 @@ Note: some of the new features are only available with certain drivers.
<li>GL_OES_texture_half_float on all r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe</li>
<li>GL_OES_texture_float_linear on all r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe</li>
<li>GL_OES_texture_half_float_linear on all r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe</li>
<li>GL_EXT_draw_buffers2 on a4xx</li>
<li>GLX_ARB_create_context_robustness on r600, radeonsi</li>
<li>EGL_EXT_create_context_robustness on r600, radeonsi</li>
<li>EGL_KHR_gl_colorspace on r600, radeonsi, nv50, nvc0</li>

60
docs/relnotes/11.1.0.html Normal file
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@ -0,0 +1,60 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 11.1.0 Release Notes / TBD</h1>
<p>
Mesa 11.1.0 is a new development release.
People who are concerned with stability and reliability should stick
with a previous release or wait for Mesa 11.1.1.
</p>
<p>
Mesa 11.1.0 implements the OpenGL 4.1 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.1. OpenGL
4.1 is <strong>only</strong> available if requested at context creation
because compatibility contexts are not supported.
</p>
<h2>SHA256 checksums</h2>
<pre>
TBD.
</pre>
<h2>New features</h2>
<p>
Note: some of the new features are only available with certain drivers.
</p>
<ul>
TBD.
</ul>
<h2>Bug fixes</h2>
TBD.
<h2>Changes</h2>
TBD.
</div>
</body>
</html>

294
include/GL/glext.h
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@ -6,7 +6,7 @@ extern "C" {
#endif
/*
** Copyright (c) 2013-2014 The Khronos Group Inc.
** Copyright (c) 2013-2015 The Khronos Group Inc.
**
** Permission is hereby granted, free of charge, to any person obtaining a
** copy of this software and/or associated documentation files (the
@ -33,7 +33,7 @@ extern "C" {
** used to make the header, and the header can be found at
** http://www.opengl.org/registry/
**
** Khronos $Revision: 29735 $ on $Date: 2015-02-02 19:00:01 -0800 (Mon, 02 Feb 2015) $
** Khronos $Revision: 31811 $ on $Date: 2015-08-10 17:01:11 +1000 (Mon, 10 Aug 2015) $
*/
#if defined(_WIN32) && !defined(APIENTRY) && !defined(__CYGWIN__) && !defined(__SCITECH_SNAP__)
@ -53,7 +53,7 @@ extern "C" {
#define GLAPI extern
#endif
#define GL_GLEXT_VERSION 20150202
#define GL_GLEXT_VERSION 20150809
/* Generated C header for:
* API: gl
@ -1041,6 +1041,22 @@ typedef unsigned short GLhalf;
#define GL_COLOR_ATTACHMENT13 0x8CED
#define GL_COLOR_ATTACHMENT14 0x8CEE
#define GL_COLOR_ATTACHMENT15 0x8CEF
#define GL_COLOR_ATTACHMENT16 0x8CF0
#define GL_COLOR_ATTACHMENT17 0x8CF1
#define GL_COLOR_ATTACHMENT18 0x8CF2
#define GL_COLOR_ATTACHMENT19 0x8CF3
#define GL_COLOR_ATTACHMENT20 0x8CF4
#define GL_COLOR_ATTACHMENT21 0x8CF5
#define GL_COLOR_ATTACHMENT22 0x8CF6
#define GL_COLOR_ATTACHMENT23 0x8CF7
#define GL_COLOR_ATTACHMENT24 0x8CF8
#define GL_COLOR_ATTACHMENT25 0x8CF9
#define GL_COLOR_ATTACHMENT26 0x8CFA
#define GL_COLOR_ATTACHMENT27 0x8CFB
#define GL_COLOR_ATTACHMENT28 0x8CFC
#define GL_COLOR_ATTACHMENT29 0x8CFD
#define GL_COLOR_ATTACHMENT30 0x8CFE
#define GL_COLOR_ATTACHMENT31 0x8CFF
#define GL_DEPTH_ATTACHMENT 0x8D00
#define GL_STENCIL_ATTACHMENT 0x8D20
#define GL_FRAMEBUFFER 0x8D40
@ -2859,6 +2875,17 @@ GLAPI void APIENTRY glTextureBarrier (void);
#define GL_ARB_ES3_1_compatibility 1
#endif /* GL_ARB_ES3_1_compatibility */
#ifndef GL_ARB_ES3_2_compatibility
#define GL_ARB_ES3_2_compatibility 1
#define GL_PRIMITIVE_BOUNDING_BOX_ARB 0x92BE
#define GL_MULTISAMPLE_LINE_WIDTH_RANGE_ARB 0x9381
#define GL_MULTISAMPLE_LINE_WIDTH_GRANULARITY_ARB 0x9382
typedef void (APIENTRYP PFNGLPRIMITIVEBOUNDINGBOXARBPROC) (GLfloat minX, GLfloat minY, GLfloat minZ, GLfloat minW, GLfloat maxX, GLfloat maxY, GLfloat maxZ, GLfloat maxW);
#ifdef GL_GLEXT_PROTOTYPES
GLAPI void APIENTRY glPrimitiveBoundingBoxARB (GLfloat minX, GLfloat minY, GLfloat minZ, GLfloat minW, GLfloat maxX, GLfloat maxY, GLfloat maxZ, GLfloat maxW);
#endif
#endif /* GL_ARB_ES3_2_compatibility */
#ifndef GL_ARB_ES3_compatibility
#define GL_ARB_ES3_compatibility 1
#endif /* GL_ARB_ES3_compatibility */
@ -3272,6 +3299,10 @@ GLAPI GLboolean APIENTRY glIsProgramARB (GLuint program);
#define GL_FRAGMENT_SHADER_DERIVATIVE_HINT_ARB 0x8B8B
#endif /* GL_ARB_fragment_shader */
#ifndef GL_ARB_fragment_shader_interlock
#define GL_ARB_fragment_shader_interlock 1
#endif /* GL_ARB_fragment_shader_interlock */
#ifndef GL_ARB_framebuffer_no_attachments
#define GL_ARB_framebuffer_no_attachments 1
#endif /* GL_ARB_framebuffer_no_attachments */
@ -3332,6 +3363,91 @@ GLAPI void APIENTRY glFramebufferTextureFaceARB (GLenum target, GLenum attachmen
#define GL_ARB_gpu_shader_fp64 1
#endif /* GL_ARB_gpu_shader_fp64 */
#ifndef GL_ARB_gpu_shader_int64
#define GL_ARB_gpu_shader_int64 1
#define GL_INT64_ARB 0x140E
#define GL_INT64_VEC2_ARB 0x8FE9
#define GL_INT64_VEC3_ARB 0x8FEA
#define GL_INT64_VEC4_ARB 0x8FEB
#define GL_UNSIGNED_INT64_VEC2_ARB 0x8FF5
#define GL_UNSIGNED_INT64_VEC3_ARB 0x8FF6
#define GL_UNSIGNED_INT64_VEC4_ARB 0x8FF7
typedef void (APIENTRYP PFNGLUNIFORM1I64ARBPROC) (GLint location, GLint64 x);
typedef void (APIENTRYP PFNGLUNIFORM2I64ARBPROC) (GLint location, GLint64 x, GLint64 y);
typedef void (APIENTRYP PFNGLUNIFORM3I64ARBPROC) (GLint location, GLint64 x, GLint64 y, GLint64 z);
typedef void (APIENTRYP PFNGLUNIFORM4I64ARBPROC) (GLint location, GLint64 x, GLint64 y, GLint64 z, GLint64 w);
typedef void (APIENTRYP PFNGLUNIFORM1I64VARBPROC) (GLint location, GLsizei count, const GLint64 *value);
typedef void (APIENTRYP PFNGLUNIFORM2I64VARBPROC) (GLint location, GLsizei count, const GLint64 *value);
typedef void (APIENTRYP PFNGLUNIFORM3I64VARBPROC) (GLint location, GLsizei count, const GLint64 *value);
typedef void (APIENTRYP PFNGLUNIFORM4I64VARBPROC) (GLint location, GLsizei count, const GLint64 *value);
typedef void (APIENTRYP PFNGLUNIFORM1UI64ARBPROC) (GLint location, GLuint64 x);
typedef void (APIENTRYP PFNGLUNIFORM2UI64ARBPROC) (GLint location, GLuint64 x, GLuint64 y);
typedef void (APIENTRYP PFNGLUNIFORM3UI64ARBPROC) (GLint location, GLuint64 x, GLuint64 y, GLuint64 z);
typedef void (APIENTRYP PFNGLUNIFORM4UI64ARBPROC) (GLint location, GLuint64 x, GLuint64 y, GLuint64 z, GLuint64 w);
typedef void (APIENTRYP PFNGLUNIFORM1UI64VARBPROC) (GLint location, GLsizei count, const GLuint64 *value);
typedef void (APIENTRYP PFNGLUNIFORM2UI64VARBPROC) (GLint location, GLsizei count, const GLuint64 *value);
typedef void (APIENTRYP PFNGLUNIFORM3UI64VARBPROC) (GLint location, GLsizei count, const GLuint64 *value);
typedef void (APIENTRYP PFNGLUNIFORM4UI64VARBPROC) (GLint location, GLsizei count, const GLuint64 *value);
typedef void (APIENTRYP PFNGLGETUNIFORMI64VARBPROC) (GLuint program, GLint location, GLint64 *params);
typedef void (APIENTRYP PFNGLGETUNIFORMUI64VARBPROC) (GLuint program, GLint location, GLuint64 *params);
typedef void (APIENTRYP PFNGLGETNUNIFORMI64VARBPROC) (GLuint program, GLint location, GLsizei bufSize, GLint64 *params);
typedef void (APIENTRYP PFNGLGETNUNIFORMUI64VARBPROC) (GLuint program, GLint location, GLsizei bufSize, GLuint64 *params);
typedef void (APIENTRYP PFNGLPROGRAMUNIFORM1I64ARBPROC) (GLuint program, GLint location, GLint64 x);
typedef void (APIENTRYP PFNGLPROGRAMUNIFORM2I64ARBPROC) (GLuint program, GLint location, GLint64 x, GLint64 y);
typedef void (APIENTRYP PFNGLPROGRAMUNIFORM3I64ARBPROC) (GLuint program, GLint location, GLint64 x, GLint64 y, GLint64 z);
typedef void (APIENTRYP PFNGLPROGRAMUNIFORM4I64ARBPROC) (GLuint program, GLint location, GLint64 x, GLint64 y, GLint64 z, GLint64 w);
typedef void (APIENTRYP PFNGLPROGRAMUNIFORM1I64VARBPROC) (GLuint program, GLint location, GLsizei count, const GLint64 *value);
typedef void (APIENTRYP PFNGLPROGRAMUNIFORM2I64VARBPROC) (GLuint program, GLint location, GLsizei count, const GLint64 *value);
typedef void (APIENTRYP PFNGLPROGRAMUNIFORM3I64VARBPROC) (GLuint program, GLint location, GLsizei count, const GLint64 *value);
typedef void (APIENTRYP PFNGLPROGRAMUNIFORM4I64VARBPROC) (GLuint program, GLint location, GLsizei count, const GLint64 *value);
typedef void (APIENTRYP PFNGLPROGRAMUNIFORM1UI64ARBPROC) (GLuint program, GLint location, GLuint64 x);
typedef void (APIENTRYP PFNGLPROGRAMUNIFORM2UI64ARBPROC) (GLuint program, GLint location, GLuint64 x, GLuint64 y);
typedef void (APIENTRYP PFNGLPROGRAMUNIFORM3UI64ARBPROC) (GLuint program, GLint location, GLuint64 x, GLuint64 y, GLuint64 z);
typedef void (APIENTRYP PFNGLPROGRAMUNIFORM4UI64ARBPROC) (GLuint program, GLint location, GLuint64 x, GLuint64 y, GLuint64 z, GLuint64 w);
typedef void (APIENTRYP PFNGLPROGRAMUNIFORM1UI64VARBPROC) (GLuint program, GLint location, GLsizei count, const GLuint64 *value);
typedef void (APIENTRYP PFNGLPROGRAMUNIFORM2UI64VARBPROC) (GLuint program, GLint location, GLsizei count, const GLuint64 *value);
typedef void (APIENTRYP PFNGLPROGRAMUNIFORM3UI64VARBPROC) (GLuint program, GLint location, GLsizei count, const GLuint64 *value);
typedef void (APIENTRYP PFNGLPROGRAMUNIFORM4UI64VARBPROC) (GLuint program, GLint location, GLsizei count, const GLuint64 *value);
#ifdef GL_GLEXT_PROTOTYPES
GLAPI void APIENTRY glUniform1i64ARB (GLint location, GLint64 x);
GLAPI void APIENTRY glUniform2i64ARB (GLint location, GLint64 x, GLint64 y);
GLAPI void APIENTRY glUniform3i64ARB (GLint location, GLint64 x, GLint64 y, GLint64 z);
GLAPI void APIENTRY glUniform4i64ARB (GLint location, GLint64 x, GLint64 y, GLint64 z, GLint64 w);
GLAPI void APIENTRY glUniform1i64vARB (GLint location, GLsizei count, const GLint64 *value);
GLAPI void APIENTRY glUniform2i64vARB (GLint location, GLsizei count, const GLint64 *value);
GLAPI void APIENTRY glUniform3i64vARB (GLint location, GLsizei count, const GLint64 *value);
GLAPI void APIENTRY glUniform4i64vARB (GLint location, GLsizei count, const GLint64 *value);
GLAPI void APIENTRY glUniform1ui64ARB (GLint location, GLuint64 x);
GLAPI void APIENTRY glUniform2ui64ARB (GLint location, GLuint64 x, GLuint64 y);
GLAPI void APIENTRY glUniform3ui64ARB (GLint location, GLuint64 x, GLuint64 y, GLuint64 z);
GLAPI void APIENTRY glUniform4ui64ARB (GLint location, GLuint64 x, GLuint64 y, GLuint64 z, GLuint64 w);
GLAPI void APIENTRY glUniform1ui64vARB (GLint location, GLsizei count, const GLuint64 *value);
GLAPI void APIENTRY glUniform2ui64vARB (GLint location, GLsizei count, const GLuint64 *value);
GLAPI void APIENTRY glUniform3ui64vARB (GLint location, GLsizei count, const GLuint64 *value);
GLAPI void APIENTRY glUniform4ui64vARB (GLint location, GLsizei count, const GLuint64 *value);
GLAPI void APIENTRY glGetUniformi64vARB (GLuint program, GLint location, GLint64 *params);
GLAPI void APIENTRY glGetUniformui64vARB (GLuint program, GLint location, GLuint64 *params);
GLAPI void APIENTRY glGetnUniformi64vARB (GLuint program, GLint location, GLsizei bufSize, GLint64 *params);
GLAPI void APIENTRY glGetnUniformui64vARB (GLuint program, GLint location, GLsizei bufSize, GLuint64 *params);
GLAPI void APIENTRY glProgramUniform1i64ARB (GLuint program, GLint location, GLint64 x);
GLAPI void APIENTRY glProgramUniform2i64ARB (GLuint program, GLint location, GLint64 x, GLint64 y);
GLAPI void APIENTRY glProgramUniform3i64ARB (GLuint program, GLint location, GLint64 x, GLint64 y, GLint64 z);
GLAPI void APIENTRY glProgramUniform4i64ARB (GLuint program, GLint location, GLint64 x, GLint64 y, GLint64 z, GLint64 w);
GLAPI void APIENTRY glProgramUniform1i64vARB (GLuint program, GLint location, GLsizei count, const GLint64 *value);
GLAPI void APIENTRY glProgramUniform2i64vARB (GLuint program, GLint location, GLsizei count, const GLint64 *value);
GLAPI void APIENTRY glProgramUniform3i64vARB (GLuint program, GLint location, GLsizei count, const GLint64 *value);
GLAPI void APIENTRY glProgramUniform4i64vARB (GLuint program, GLint location, GLsizei count, const GLint64 *value);
GLAPI void APIENTRY glProgramUniform1ui64ARB (GLuint program, GLint location, GLuint64 x);
GLAPI void APIENTRY glProgramUniform2ui64ARB (GLuint program, GLint location, GLuint64 x, GLuint64 y);
GLAPI void APIENTRY glProgramUniform3ui64ARB (GLuint program, GLint location, GLuint64 x, GLuint64 y, GLuint64 z);
GLAPI void APIENTRY glProgramUniform4ui64ARB (GLuint program, GLint location, GLuint64 x, GLuint64 y, GLuint64 z, GLuint64 w);
GLAPI void APIENTRY glProgramUniform1ui64vARB (GLuint program, GLint location, GLsizei count, const GLuint64 *value);
GLAPI void APIENTRY glProgramUniform2ui64vARB (GLuint program, GLint location, GLsizei count, const GLuint64 *value);
GLAPI void APIENTRY glProgramUniform3ui64vARB (GLuint program, GLint location, GLsizei count, const GLuint64 *value);
GLAPI void APIENTRY glProgramUniform4ui64vARB (GLuint program, GLint location, GLsizei count, const GLuint64 *value);
#endif
#endif /* GL_ARB_gpu_shader_int64 */
#ifndef GL_ARB_half_float_pixel
#define GL_ARB_half_float_pixel 1
typedef unsigned short GLhalfARB;
@ -3711,6 +3827,16 @@ GLAPI void APIENTRY glGetQueryObjectuivARB (GLuint id, GLenum pname, GLuint *par
#define GL_ARB_occlusion_query2 1
#endif /* GL_ARB_occlusion_query2 */
#ifndef GL_ARB_parallel_shader_compile
#define GL_ARB_parallel_shader_compile 1
#define GL_MAX_SHADER_COMPILER_THREADS_ARB 0x91B0
#define GL_COMPLETION_STATUS_ARB 0x91B1
typedef void (APIENTRYP PFNGLMAXSHADERCOMPILERTHREADSARBPROC) (GLuint count);
#ifdef GL_GLEXT_PROTOTYPES
GLAPI void APIENTRY glMaxShaderCompilerThreadsARB (GLuint count);
#endif
#endif /* GL_ARB_parallel_shader_compile */
#ifndef GL_ARB_pipeline_statistics_query
#define GL_ARB_pipeline_statistics_query 1
#define GL_VERTICES_SUBMITTED_ARB 0x82EE
@ -3753,6 +3879,10 @@ GLAPI void APIENTRY glPointParameterfvARB (GLenum pname, const GLfloat *params);
#define GL_COORD_REPLACE_ARB 0x8862
#endif /* GL_ARB_point_sprite */
#ifndef GL_ARB_post_depth_coverage
#define GL_ARB_post_depth_coverage 1
#endif /* GL_ARB_post_depth_coverage */
#ifndef GL_ARB_program_interface_query
#define GL_ARB_program_interface_query 1
#endif /* GL_ARB_program_interface_query */
@ -3826,6 +3956,26 @@ GLAPI void APIENTRY glGetnMinmaxARB (GLenum target, GLboolean reset, GLenum form
#define GL_ARB_robustness_isolation 1
#endif /* GL_ARB_robustness_isolation */
#ifndef GL_ARB_sample_locations
#define GL_ARB_sample_locations 1
#define GL_SAMPLE_LOCATION_SUBPIXEL_BITS_ARB 0x933D
#define GL_SAMPLE_LOCATION_PIXEL_GRID_WIDTH_ARB 0x933E
#define GL_SAMPLE_LOCATION_PIXEL_GRID_HEIGHT_ARB 0x933F
#define GL_PROGRAMMABLE_SAMPLE_LOCATION_TABLE_SIZE_ARB 0x9340
#define GL_SAMPLE_LOCATION_ARB 0x8E50
#define GL_PROGRAMMABLE_SAMPLE_LOCATION_ARB 0x9341
#define GL_FRAMEBUFFER_PROGRAMMABLE_SAMPLE_LOCATIONS_ARB 0x9342
#define GL_FRAMEBUFFER_SAMPLE_LOCATION_PIXEL_GRID_ARB 0x9343
typedef void (APIENTRYP PFNGLFRAMEBUFFERSAMPLELOCATIONSFVARBPROC) (GLenum target, GLuint start, GLsizei count, const GLfloat *v);
typedef void (APIENTRYP PFNGLNAMEDFRAMEBUFFERSAMPLELOCATIONSFVARBPROC) (GLuint framebuffer, GLuint start, GLsizei count, const GLfloat *v);
typedef void (APIENTRYP PFNGLEVALUATEDEPTHVALUESARBPROC) (void);
#ifdef GL_GLEXT_PROTOTYPES
GLAPI void APIENTRY glFramebufferSampleLocationsfvARB (GLenum target, GLuint start, GLsizei count, const GLfloat *v);
GLAPI void APIENTRY glNamedFramebufferSampleLocationsfvARB (GLuint framebuffer, GLuint start, GLsizei count, const GLfloat *v);
GLAPI void APIENTRY glEvaluateDepthValuesARB (void);
#endif
#endif /* GL_ARB_sample_locations */
#ifndef GL_ARB_sample_shading
#define GL_ARB_sample_shading 1
#define GL_SAMPLE_SHADING_ARB 0x8C36
@ -3852,14 +4002,26 @@ GLAPI void APIENTRY glMinSampleShadingARB (GLfloat value);
#define GL_ARB_separate_shader_objects 1
#endif /* GL_ARB_separate_shader_objects */
#ifndef GL_ARB_shader_atomic_counter_ops
#define GL_ARB_shader_atomic_counter_ops 1
#endif /* GL_ARB_shader_atomic_counter_ops */
#ifndef GL_ARB_shader_atomic_counters
#define GL_ARB_shader_atomic_counters 1
#endif /* GL_ARB_shader_atomic_counters */
#ifndef GL_ARB_shader_ballot
#define GL_ARB_shader_ballot 1
#endif /* GL_ARB_shader_ballot */
#ifndef GL_ARB_shader_bit_encoding
#define GL_ARB_shader_bit_encoding 1
#endif /* GL_ARB_shader_bit_encoding */
#ifndef GL_ARB_shader_clock
#define GL_ARB_shader_clock 1
#endif /* GL_ARB_shader_clock */
#ifndef GL_ARB_shader_draw_parameters
#define GL_ARB_shader_draw_parameters 1
#endif /* GL_ARB_shader_draw_parameters */
@ -4029,6 +4191,10 @@ GLAPI void APIENTRY glGetShaderSourceARB (GLhandleARB obj, GLsizei maxLength, GL
#define GL_ARB_shader_texture_lod 1
#endif /* GL_ARB_shader_texture_lod */
#ifndef GL_ARB_shader_viewport_layer_array
#define GL_ARB_shader_viewport_layer_array 1
#endif /* GL_ARB_shader_viewport_layer_array */
#ifndef GL_ARB_shading_language_100
#define GL_ARB_shading_language_100 1
#define GL_SHADING_LANGUAGE_VERSION_ARB 0x8B8C
@ -4102,12 +4268,20 @@ GLAPI void APIENTRY glNamedBufferPageCommitmentARB (GLuint buffer, GLintptr offs
#define GL_MAX_SPARSE_3D_TEXTURE_SIZE_ARB 0x9199
#define GL_MAX_SPARSE_ARRAY_TEXTURE_LAYERS_ARB 0x919A
#define GL_SPARSE_TEXTURE_FULL_ARRAY_CUBE_MIPMAPS_ARB 0x91A9
typedef void (APIENTRYP PFNGLTEXPAGECOMMITMENTARBPROC) (GLenum target, GLint level, GLint xoffset, GLint yoffset, GLint zoffset, GLsizei width, GLsizei height, GLsizei depth, GLboolean resident);
typedef void (APIENTRYP PFNGLTEXPAGECOMMITMENTARBPROC) (GLenum target, GLint level, GLint xoffset, GLint yoffset, GLint zoffset, GLsizei width, GLsizei height, GLsizei depth, GLboolean commit);
#ifdef GL_GLEXT_PROTOTYPES
GLAPI void APIENTRY glTexPageCommitmentARB (GLenum target, GLint level, GLint xoffset, GLint yoffset, GLint zoffset, GLsizei width, GLsizei height, GLsizei depth, GLboolean resident);
GLAPI void APIENTRY glTexPageCommitmentARB (GLenum target, GLint level, GLint xoffset, GLint yoffset, GLint zoffset, GLsizei width, GLsizei height, GLsizei depth, GLboolean commit);
#endif
#endif /* GL_ARB_sparse_texture */
#ifndef GL_ARB_sparse_texture2
#define GL_ARB_sparse_texture2 1
#endif /* GL_ARB_sparse_texture2 */
#ifndef GL_ARB_sparse_texture_clamp
#define GL_ARB_sparse_texture_clamp 1
#endif /* GL_ARB_sparse_texture_clamp */
#ifndef GL_ARB_stencil_texturing
#define GL_ARB_stencil_texturing 1
#endif /* GL_ARB_stencil_texturing */
@ -4260,6 +4434,12 @@ GLAPI void APIENTRY glGetCompressedTexImageARB (GLenum target, GLint level, void
#define GL_DOT3_RGBA_ARB 0x86AF
#endif /* GL_ARB_texture_env_dot3 */
#ifndef GL_ARB_texture_filter_minmax
#define GL_ARB_texture_filter_minmax 1
#define GL_TEXTURE_REDUCTION_MODE_ARB 0x9366
#define GL_WEIGHTED_AVERAGE_ARB 0x9367
#endif /* GL_ARB_texture_filter_minmax */
#ifndef GL_ARB_texture_float
#define GL_ARB_texture_float 1
#define GL_TEXTURE_RED_TYPE_ARB 0x8C10
@ -4754,6 +4934,11 @@ GLAPI void APIENTRY glBlendBarrierKHR (void);
#define GL_KHR_debug 1
#endif /* GL_KHR_debug */
#ifndef GL_KHR_no_error
#define GL_KHR_no_error 1
#define GL_CONTEXT_FLAG_NO_ERROR_BIT_KHR 0x00000008
#endif /* GL_KHR_no_error */
#ifndef GL_KHR_robust_buffer_access_behavior
#define GL_KHR_robust_buffer_access_behavior 1
#endif /* GL_KHR_robust_buffer_access_behavior */
@ -4896,7 +5081,6 @@ typedef void (APIENTRYP PFNGLPOINTPARAMETERXVOESPROC) (GLenum pname, const GLfix
typedef void (APIENTRYP PFNGLPOINTSIZEXOESPROC) (GLfixed size);
typedef void (APIENTRYP PFNGLPOLYGONOFFSETXOESPROC) (GLfixed factor, GLfixed units);
typedef void (APIENTRYP PFNGLROTATEXOESPROC) (GLfixed angle, GLfixed x, GLfixed y, GLfixed z);
typedef void (APIENTRYP PFNGLSAMPLECOVERAGEOESPROC) (GLfixed value, GLboolean invert);
typedef void (APIENTRYP PFNGLSCALEXOESPROC) (GLfixed x, GLfixed y, GLfixed z);
typedef void (APIENTRYP PFNGLTEXENVXOESPROC) (GLenum target, GLenum pname, GLfixed param);
typedef void (APIENTRYP PFNGLTEXENVXVOESPROC) (GLenum target, GLenum pname, const GLfixed *params);
@ -5001,7 +5185,6 @@ GLAPI void APIENTRY glPointParameterxvOES (GLenum pname, const GLfixed *params);
GLAPI void APIENTRY glPointSizexOES (GLfixed size);
GLAPI void APIENTRY glPolygonOffsetxOES (GLfixed factor, GLfixed units);
GLAPI void APIENTRY glRotatexOES (GLfixed angle, GLfixed x, GLfixed y, GLfixed z);
GLAPI void APIENTRY glSampleCoverageOES (GLfixed value, GLboolean invert);
GLAPI void APIENTRY glScalexOES (GLfixed x, GLfixed y, GLfixed z);
GLAPI void APIENTRY glTexEnvxOES (GLenum target, GLenum pname, GLfixed param);
GLAPI void APIENTRY glTexEnvxvOES (GLenum target, GLenum pname, const GLfixed *params);
@ -6715,7 +6898,7 @@ typedef void (APIENTRYP PFNGLVERTEXARRAYVERTEXATTRIBLFORMATEXTPROC) (GLuint vaob
typedef void (APIENTRYP PFNGLVERTEXARRAYVERTEXATTRIBBINDINGEXTPROC) (GLuint vaobj, GLuint attribindex, GLuint bindingindex);
typedef void (APIENTRYP PFNGLVERTEXARRAYVERTEXBINDINGDIVISOREXTPROC) (GLuint vaobj, GLuint bindingindex, GLuint divisor);
typedef void (APIENTRYP PFNGLVERTEXARRAYVERTEXATTRIBLOFFSETEXTPROC) (GLuint vaobj, GLuint buffer, GLuint index, GLint size, GLenum type, GLsizei stride, GLintptr offset);
typedef void (APIENTRYP PFNGLTEXTUREPAGECOMMITMENTEXTPROC) (GLuint texture, GLint level, GLint xoffset, GLint yoffset, GLint zoffset, GLsizei width, GLsizei height, GLsizei depth, GLboolean resident);
typedef void (APIENTRYP PFNGLTEXTUREPAGECOMMITMENTEXTPROC) (GLuint texture, GLint level, GLint xoffset, GLint yoffset, GLint zoffset, GLsizei width, GLsizei height, GLsizei depth, GLboolean commit);
typedef void (APIENTRYP PFNGLVERTEXARRAYVERTEXATTRIBDIVISOREXTPROC) (GLuint vaobj, GLuint index, GLuint divisor);
#ifdef GL_GLEXT_PROTOTYPES
GLAPI void APIENTRY glMatrixLoadfEXT (GLenum mode, const GLfloat *m);
@ -6971,7 +7154,7 @@ GLAPI void APIENTRY glVertexArrayVertexAttribLFormatEXT (GLuint vaobj, GLuint at
GLAPI void APIENTRY glVertexArrayVertexAttribBindingEXT (GLuint vaobj, GLuint attribindex, GLuint bindingindex);
GLAPI void APIENTRY glVertexArrayVertexBindingDivisorEXT (GLuint vaobj, GLuint bindingindex, GLuint divisor);
GLAPI void APIENTRY glVertexArrayVertexAttribLOffsetEXT (GLuint vaobj, GLuint buffer, GLuint index, GLint size, GLenum type, GLsizei stride, GLintptr offset);
GLAPI void APIENTRY glTexturePageCommitmentEXT (GLuint texture, GLint level, GLint xoffset, GLint yoffset, GLint zoffset, GLsizei width, GLsizei height, GLsizei depth, GLboolean resident);
GLAPI void APIENTRY glTexturePageCommitmentEXT (GLuint texture, GLint level, GLint xoffset, GLint yoffset, GLint zoffset, GLsizei width, GLsizei height, GLsizei depth, GLboolean commit);
GLAPI void APIENTRY glVertexArrayVertexAttribDivisorEXT (GLuint vaobj, GLuint index, GLuint divisor);
#endif
#endif /* GL_EXT_direct_state_access */
@ -8635,6 +8818,14 @@ GLAPI void APIENTRY glBlendFuncSeparateINGR (GLenum sfactorRGB, GLenum dfactorRG
#define GL_INTEL_fragment_shader_ordering 1
#endif /* GL_INTEL_fragment_shader_ordering */
#ifndef GL_INTEL_framebuffer_CMAA
#define GL_INTEL_framebuffer_CMAA 1
typedef void (APIENTRYP PFNGLAPPLYFRAMEBUFFERATTACHMENTCMAAINTELPROC) (void);
#ifdef GL_GLEXT_PROTOTYPES
GLAPI void APIENTRY glApplyFramebufferAttachmentCMAAINTEL (void);
#endif
#endif /* GL_INTEL_framebuffer_CMAA */
#ifndef GL_INTEL_map_texture
#define GL_INTEL_map_texture 1
#define GL_TEXTURE_MEMORY_LAYOUT_INTEL 0x83FF
@ -8939,6 +9130,65 @@ GLAPI void APIENTRY glBlendBarrierNV (void);
#define GL_NV_blend_square 1
#endif /* GL_NV_blend_square */
#ifndef GL_NV_command_list
#define GL_NV_command_list 1
#define GL_TERMINATE_SEQUENCE_COMMAND_NV 0x0000
#define GL_NOP_COMMAND_NV 0x0001
#define GL_DRAW_ELEMENTS_COMMAND_NV 0x0002
#define GL_DRAW_ARRAYS_COMMAND_NV 0x0003
#define GL_DRAW_ELEMENTS_STRIP_COMMAND_NV 0x0004
#define GL_DRAW_ARRAYS_STRIP_COMMAND_NV 0x0005
#define GL_DRAW_ELEMENTS_INSTANCED_COMMAND_NV 0x0006
#define GL_DRAW_ARRAYS_INSTANCED_COMMAND_NV 0x0007
#define GL_ELEMENT_ADDRESS_COMMAND_NV 0x0008
#define GL_ATTRIBUTE_ADDRESS_COMMAND_NV 0x0009
#define GL_UNIFORM_ADDRESS_COMMAND_NV 0x000A
#define GL_BLEND_COLOR_COMMAND_NV 0x000B
#define GL_STENCIL_REF_COMMAND_NV 0x000C
#define GL_LINE_WIDTH_COMMAND_NV 0x000D
#define GL_POLYGON_OFFSET_COMMAND_NV 0x000E
#define GL_ALPHA_REF_COMMAND_NV 0x000F
#define GL_VIEWPORT_COMMAND_NV 0x0010
#define GL_SCISSOR_COMMAND_NV 0x0011
#define GL_FRONT_FACE_COMMAND_NV 0x0012
typedef void (APIENTRYP PFNGLCREATESTATESNVPROC) (GLsizei n, GLuint *states);
typedef void (APIENTRYP PFNGLDELETESTATESNVPROC) (GLsizei n, const GLuint *states);
typedef GLboolean (APIENTRYP PFNGLISSTATENVPROC) (GLuint state);
typedef void (APIENTRYP PFNGLSTATECAPTURENVPROC) (GLuint state, GLenum mode);
typedef GLuint (APIENTRYP PFNGLGETCOMMANDHEADERNVPROC) (GLenum tokenID, GLuint size);
typedef GLushort (APIENTRYP PFNGLGETSTAGEINDEXNVPROC) (GLenum shadertype);
typedef void (APIENTRYP PFNGLDRAWCOMMANDSNVPROC) (GLenum primitiveMode, GLuint buffer, const GLintptr *indirects, const GLsizei *sizes, GLuint count);
typedef void (APIENTRYP PFNGLDRAWCOMMANDSADDRESSNVPROC) (GLenum primitiveMode, const GLuint64 *indirects, const GLsizei *sizes, GLuint count);
typedef void (APIENTRYP PFNGLDRAWCOMMANDSSTATESNVPROC) (GLuint buffer, const GLintptr *indirects, const GLsizei *sizes, const GLuint *states, const GLuint *fbos, GLuint count);
typedef void (APIENTRYP PFNGLDRAWCOMMANDSSTATESADDRESSNVPROC) (const GLuint64 *indirects, const GLsizei *sizes, const GLuint *states, const GLuint *fbos, GLuint count);
typedef void (APIENTRYP PFNGLCREATECOMMANDLISTSNVPROC) (GLsizei n, GLuint *lists);
typedef void (APIENTRYP PFNGLDELETECOMMANDLISTSNVPROC) (GLsizei n, const GLuint *lists);
typedef GLboolean (APIENTRYP PFNGLISCOMMANDLISTNVPROC) (GLuint list);
typedef void (APIENTRYP PFNGLLISTDRAWCOMMANDSSTATESCLIENTNVPROC) (GLuint list, GLuint segment, const void **indirects, const GLsizei *sizes, const GLuint *states, const GLuint *fbos, GLuint count);
typedef void (APIENTRYP PFNGLCOMMANDLISTSEGMENTSNVPROC) (GLuint list, GLuint segments);
typedef void (APIENTRYP PFNGLCOMPILECOMMANDLISTNVPROC) (GLuint list);
typedef void (APIENTRYP PFNGLCALLCOMMANDLISTNVPROC) (GLuint list);
#ifdef GL_GLEXT_PROTOTYPES
GLAPI void APIENTRY glCreateStatesNV (GLsizei n, GLuint *states);
GLAPI void APIENTRY glDeleteStatesNV (GLsizei n, const GLuint *states);
GLAPI GLboolean APIENTRY glIsStateNV (GLuint state);
GLAPI void APIENTRY glStateCaptureNV (GLuint state, GLenum mode);
GLAPI GLuint APIENTRY glGetCommandHeaderNV (GLenum tokenID, GLuint size);
GLAPI GLushort APIENTRY glGetStageIndexNV (GLenum shadertype);
GLAPI void APIENTRY glDrawCommandsNV (GLenum primitiveMode, GLuint buffer, const GLintptr *indirects, const GLsizei *sizes, GLuint count);
GLAPI void APIENTRY glDrawCommandsAddressNV (GLenum primitiveMode, const GLuint64 *indirects, const GLsizei *sizes, GLuint count);
GLAPI void APIENTRY glDrawCommandsStatesNV (GLuint buffer, const GLintptr *indirects, const GLsizei *sizes, const GLuint *states, const GLuint *fbos, GLuint count);
GLAPI void APIENTRY glDrawCommandsStatesAddressNV (const GLuint64 *indirects, const GLsizei *sizes, const GLuint *states, const GLuint *fbos, GLuint count);
GLAPI void APIENTRY glCreateCommandListsNV (GLsizei n, GLuint *lists);
GLAPI void APIENTRY glDeleteCommandListsNV (GLsizei n, const GLuint *lists);
GLAPI GLboolean APIENTRY glIsCommandListNV (GLuint list);
GLAPI void APIENTRY glListDrawCommandsStatesClientNV (GLuint list, GLuint segment, const void **indirects, const GLsizei *sizes, const GLuint *states, const GLuint *fbos, GLuint count);
GLAPI void APIENTRY glCommandListSegmentsNV (GLuint list, GLuint segments);
GLAPI void APIENTRY glCompileCommandListNV (GLuint list);
GLAPI void APIENTRY glCallCommandListNV (GLuint list);
#endif
#endif /* GL_NV_command_list */
#ifndef GL_NV_compute_program5
#define GL_NV_compute_program5 1
#define GL_COMPUTE_PROGRAM_NV 0x90FB
@ -8971,6 +9221,17 @@ GLAPI void APIENTRY glSubpixelPrecisionBiasNV (GLuint xbits, GLuint ybits);
#endif
#endif /* GL_NV_conservative_raster */
#ifndef GL_NV_conservative_raster_dilate
#define GL_NV_conservative_raster_dilate 1
#define GL_CONSERVATIVE_RASTER_DILATE_NV 0x9379
#define GL_CONSERVATIVE_RASTER_DILATE_RANGE_NV 0x937A
#define GL_CONSERVATIVE_RASTER_DILATE_GRANULARITY_NV 0x937B
typedef void (APIENTRYP PFNGLCONSERVATIVERASTERPARAMETERFNVPROC) (GLenum pname, GLfloat value);
#ifdef GL_GLEXT_PROTOTYPES
GLAPI void APIENTRY glConservativeRasterParameterfNV (GLenum pname, GLfloat value);
#endif
#endif /* GL_NV_conservative_raster_dilate */
#ifndef GL_NV_copy_depth_to_color
#define GL_NV_copy_depth_to_color 1
#define GL_DEPTH_STENCIL_TO_RGBA_NV 0x886E
@ -10850,6 +11111,21 @@ GLAPI void APIENTRY glVideoCaptureStreamParameterdvNV (GLuint video_capture_slot
#define GL_FORMAT_SUBSAMPLE_244_244_OML 0x8983
#endif /* GL_OML_subsample */
#ifndef GL_OVR_multiview
#define GL_OVR_multiview 1
#define GL_FRAMEBUFFER_ATTACHMENT_TEXTURE_NUM_VIEWS_OVR 0x9630
#define GL_FRAMEBUFFER_ATTACHMENT_TEXTURE_BASE_VIEW_INDEX_OVR 0x9632
#define GL_MAX_VIEWS_OVR 0x9631
typedef void (APIENTRYP PFNGLFRAMEBUFFERTEXTUREMULTIVIEWOVRPROC) (GLenum target, GLenum attachment, GLuint texture, GLint level, GLint baseViewIndex, GLsizei numViews);
#ifdef GL_GLEXT_PROTOTYPES
GLAPI void APIENTRY glFramebufferTextureMultiviewOVR (GLenum target, GLenum attachment, GLuint texture, GLint level, GLint baseViewIndex, GLsizei numViews);
#endif
#endif /* GL_OVR_multiview */
#ifndef GL_OVR_multiview2
#define GL_OVR_multiview2 1
#endif /* GL_OVR_multiview2 */
#ifndef GL_PGI_misc_hints
#define GL_PGI_misc_hints 1
#define GL_PREFER_DOUBLEBUFFER_HINT_PGI 0x1A1F8

1
scons/gallium.py
View file

@ -300,6 +300,7 @@ def generate(env):
# C preprocessor options
cppdefines = []
cppdefines += ['__STDC_LIMIT_MACROS']
if env['build'] in ('debug', 'checked'):
cppdefines += ['DEBUG']
else:

1
src/egl/SConscript
View file

@ -15,7 +15,6 @@ env.Append(CPPPATH = [
# parse Makefile.sources
egl_sources = env.ParseSourceList('Makefile.sources', 'LIBEGL_C_FILES')
egl_sources.append(env.ParseSourceList('Makefile.sources', 'dri2_backend_core_FILES'))
env.Append(CPPDEFINES = [
'_EGL_NATIVE_PLATFORM=_EGL_PLATFORM_HAIKU',

10
src/egl/drivers/dri2/platform_drm.c
View file

@ -68,7 +68,7 @@ release_buffer(struct gbm_surface *_surf, struct gbm_bo *bo)
{
struct gbm_dri_surface *surf = (struct gbm_dri_surface *) _surf;
struct dri2_egl_surface *dri2_surf = surf->dri_private;
int i;
unsigned i;
for (i = 0; i < ARRAY_SIZE(dri2_surf->color_buffers); i++) {
if (dri2_surf->color_buffers[i].bo == bo) {
@ -82,7 +82,7 @@ has_free_buffers(struct gbm_surface *_surf)
{
struct gbm_dri_surface *surf = (struct gbm_dri_surface *) _surf;
struct dri2_egl_surface *dri2_surf = surf->dri_private;
int i;
unsigned i;
for (i = 0; i < ARRAY_SIZE(dri2_surf->color_buffers); i++)
if (!dri2_surf->color_buffers[i].locked)
@ -189,7 +189,7 @@ dri2_drm_destroy_surface(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *surf)
{
struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
struct dri2_egl_surface *dri2_surf = dri2_egl_surface(surf);
int i;
unsigned i;
if (!_eglPutSurface(surf))
return EGL_TRUE;
@ -218,7 +218,7 @@ get_back_bo(struct dri2_egl_surface *dri2_surf)
struct dri2_egl_display *dri2_dpy =
dri2_egl_display(dri2_surf->base.Resource.Display);
struct gbm_dri_surface *surf = dri2_surf->gbm_surf;
int i;
unsigned i;
if (dri2_surf->back == NULL) {
for (i = 0; i < ARRAY_SIZE(dri2_surf->color_buffers); i++) {
@ -414,7 +414,7 @@ dri2_drm_swap_buffers(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *draw)
{
struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
struct dri2_egl_surface *dri2_surf = dri2_egl_surface(draw);
int i;
unsigned i;
if (dri2_dpy->swrast) {
(*dri2_dpy->core->swapBuffers)(dri2_surf->dri_drawable);

4
src/egl/drivers/dri2/platform_wayland.c
View file

@ -1227,6 +1227,8 @@ dri2_wl_swrast_get_stride_for_format(int format, int w)
* Taken from weston shared/os-compatibility.c
*/
#ifndef HAVE_MKOSTEMP
static int
set_cloexec_or_close(int fd)
{
@ -1249,6 +1251,8 @@ err:
return -1;
}
#endif
/*
* Taken from weston shared/os-compatibility.c
*/

58
src/gallium/auxiliary/nir/tgsi_to_nir.c
View file

@ -24,6 +24,7 @@
#include "util/ralloc.h"
#include "glsl/nir/nir.h"
#include "glsl/nir/nir_control_flow.h"
#include "glsl/nir/nir_builder.h"
#include "glsl/list.h"
#include "glsl/shader_enums.h"
@ -307,7 +308,7 @@ ttn_emit_immediate(struct ttn_compile *c)
for (i = 0; i < 4; i++)
load_const->value.u[i] = tgsi_imm->u[i].Uint;
nir_instr_insert_after_cf_list(b->cf_node_list, &load_const->instr);
nir_builder_instr_insert(b, &load_const->instr);
}
static nir_src
@ -363,7 +364,7 @@ ttn_src_for_file_and_index(struct ttn_compile *c, unsigned file, unsigned index,
load->variables[0] = ttn_array_deref(c, load, var, offset, indirect);
nir_ssa_dest_init(&load->instr, &load->dest, 4, NULL);
nir_instr_insert_after_cf_list(b->cf_node_list, &load->instr);
nir_builder_instr_insert(b, &load->instr);
src = nir_src_for_ssa(&load->dest.ssa);
@ -414,7 +415,7 @@ ttn_src_for_file_and_index(struct ttn_compile *c, unsigned file, unsigned index,
load->num_components = ncomp;
nir_ssa_dest_init(&load->instr, &load->dest, ncomp, NULL);
nir_instr_insert_after_cf_list(b->cf_node_list, &load->instr);
nir_builder_instr_insert(b, &load->instr);
src = nir_src_for_ssa(&load->dest.ssa);
break;
@ -476,7 +477,7 @@ ttn_src_for_file_and_index(struct ttn_compile *c, unsigned file, unsigned index,
srcn++;
}
nir_ssa_dest_init(&load->instr, &load->dest, 4, NULL);
nir_instr_insert_after_cf_list(b->cf_node_list, &load->instr);
nir_builder_instr_insert(b, &load->instr);
src = nir_src_for_ssa(&load->dest.ssa);
break;
@ -552,7 +553,7 @@ ttn_get_dest(struct ttn_compile *c, struct tgsi_full_dst_register *tgsi_fdst)
load->dest = nir_dest_for_reg(reg);
nir_instr_insert_after_cf_list(b->cf_node_list, &load->instr);
nir_builder_instr_insert(b, &load->instr);
} else {
assert(!tgsi_dst->Indirect);
dest.dest.reg.reg = c->temp_regs[index].reg;
@ -667,7 +668,7 @@ ttn_alu(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
instr->src[i].src = nir_src_for_ssa(src[i]);
instr->dest = dest;
nir_instr_insert_after_cf_list(b->cf_node_list, &instr->instr);
nir_builder_instr_insert(b, &instr->instr);
}
static void
@ -683,7 +684,7 @@ ttn_move_dest_masked(nir_builder *b, nir_alu_dest dest,
mov->src[0].src = nir_src_for_ssa(def);
for (unsigned i = def->num_components; i < 4; i++)
mov->src[0].swizzle[i] = def->num_components - 1;
nir_instr_insert_after_cf_list(b->cf_node_list, &mov->instr);
nir_builder_instr_insert(b, &mov->instr);
}
static void
@ -902,7 +903,7 @@ ttn_kill(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
{
nir_intrinsic_instr *discard =
nir_intrinsic_instr_create(b->shader, nir_intrinsic_discard);
nir_instr_insert_after_cf_list(b->cf_node_list, &discard->instr);
nir_builder_instr_insert(b, &discard->instr);
}
static void
@ -912,7 +913,7 @@ ttn_kill_if(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
nir_intrinsic_instr *discard =
nir_intrinsic_instr_create(b->shader, nir_intrinsic_discard_if);
discard->src[0] = nir_src_for_ssa(cmp);
nir_instr_insert_after_cf_list(b->cf_node_list, &discard->instr);
nir_builder_instr_insert(b, &discard->instr);
}
static void
@ -976,14 +977,14 @@ static void
ttn_cont(nir_builder *b)
{
nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_continue);
nir_instr_insert_after_cf_list(b->cf_node_list, &instr->instr);
nir_builder_instr_insert(b, &instr->instr);
}
static void
ttn_brk(nir_builder *b)
{
nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_break);
nir_instr_insert_after_cf_list(b->cf_node_list, &instr->instr);
nir_builder_instr_insert(b, &instr->instr);
}
static void
@ -1279,7 +1280,7 @@ ttn_tex(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
assert(src_number == num_srcs);
nir_ssa_dest_init(&instr->instr, &instr->dest, 4, NULL);
nir_instr_insert_after_cf_list(b->cf_node_list, &instr->instr);
nir_builder_instr_insert(b, &instr->instr);
/* Resolve the writemask on the texture op. */
ttn_move_dest(b, dest, &instr->dest.ssa);
@ -1318,10 +1319,10 @@ ttn_txq(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
txs->src[0].src_type = nir_tex_src_lod;
nir_ssa_dest_init(&txs->instr, &txs->dest, 3, NULL);
nir_instr_insert_after_cf_list(b->cf_node_list, &txs->instr);
nir_builder_instr_insert(b, &txs->instr);
nir_ssa_dest_init(&qlv->instr, &qlv->dest, 1, NULL);
nir_instr_insert_after_cf_list(b->cf_node_list, &qlv->instr);
nir_builder_instr_insert(b, &qlv->instr);
ttn_move_dest_masked(b, dest, &txs->dest.ssa, TGSI_WRITEMASK_XYZ);
ttn_move_dest_masked(b, dest, &qlv->dest.ssa, TGSI_WRITEMASK_W);
@ -1730,7 +1731,7 @@ ttn_emit_instruction(struct ttn_compile *c)
store->variables[0] = ttn_array_deref(c, store, var, offset, indirect);
store->src[0] = nir_src_for_reg(dest.dest.reg.reg);
nir_instr_insert_after_cf_list(b->cf_node_list, &store->instr);
nir_builder_instr_insert(b, &store->instr);
}
}
@ -1759,11 +1760,26 @@ ttn_add_output_stores(struct ttn_compile *c)
store->const_index[0] = loc;
store->src[0].reg.reg = c->output_regs[loc].reg;
store->src[0].reg.base_offset = c->output_regs[loc].offset;
nir_instr_insert_after_cf_list(b->cf_node_list, &store->instr);
nir_builder_instr_insert(b, &store->instr);
}
}
}
static gl_shader_stage
tgsi_processor_to_shader_stage(unsigned processor)
{
switch (processor) {
case TGSI_PROCESSOR_FRAGMENT: return MESA_SHADER_FRAGMENT;
case TGSI_PROCESSOR_VERTEX: return MESA_SHADER_VERTEX;
case TGSI_PROCESSOR_GEOMETRY: return MESA_SHADER_GEOMETRY;
case TGSI_PROCESSOR_TESS_CTRL: return MESA_SHADER_TESS_CTRL;
case TGSI_PROCESSOR_TESS_EVAL: return MESA_SHADER_TESS_EVAL;
case TGSI_PROCESSOR_COMPUTE: return MESA_SHADER_COMPUTE;
default:
unreachable("invalid TGSI processor");
};
}
struct nir_shader *
tgsi_to_nir(const void *tgsi_tokens,
const nir_shader_compiler_options *options)
@ -1775,7 +1791,12 @@ tgsi_to_nir(const void *tgsi_tokens,
int ret;
c = rzalloc(NULL, struct ttn_compile);
s = nir_shader_create(NULL, options);
tgsi_scan_shader(tgsi_tokens, &scan);
c->scan = &scan;
s = nir_shader_create(NULL, tgsi_processor_to_shader_stage(scan.processor),
options);
nir_function *func = nir_function_create(s, "main");
nir_function_overload *overload = nir_function_overload_create(func);
@ -1784,9 +1805,6 @@ tgsi_to_nir(const void *tgsi_tokens,
nir_builder_init(&c->build, impl);
nir_builder_insert_after_cf_list(&c->build, &impl->body);
tgsi_scan_shader(tgsi_tokens, &scan);
c->scan = &scan;
s->num_inputs = scan.file_max[TGSI_FILE_INPUT] + 1;
s->num_uniforms = scan.const_file_max[0] + 1;
s->num_outputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;

23
src/gallium/auxiliary/tgsi/tgsi_text.c
View file

@ -259,7 +259,7 @@ struct translate_ctx
struct tgsi_token *tokens_end;
struct tgsi_header *header;
unsigned processor : 4;
int implied_array_size : 5;
unsigned implied_array_size : 6;
unsigned num_immediates;
};
@ -675,6 +675,9 @@ parse_register_dcl(
eat_opt_white( &cur );
if (cur[0] == '[') {
bool is_in = *file == TGSI_FILE_INPUT;
bool is_out = *file == TGSI_FILE_OUTPUT;
++cur;
ctx->cur = cur;
if (!parse_register_dcl_bracket( ctx, &brackets[1] ))
@ -684,7 +687,11 @@ parse_register_dcl(
* input primitive. so we want to declare just
* the index relevant to the semantics which is in
* the second bracket */
if (ctx->processor == TGSI_PROCESSOR_GEOMETRY && *file == TGSI_FILE_INPUT) {
/* tessellation has similar constraints to geometry shader */
if ((ctx->processor == TGSI_PROCESSOR_GEOMETRY && is_in) ||
(ctx->processor == TGSI_PROCESSOR_TESS_EVAL && is_in) ||
(ctx->processor == TGSI_PROCESSOR_TESS_CTRL && (is_in || is_out))) {
brackets[0] = brackets[1];
*num_brackets = 1;
} else {
@ -740,6 +747,14 @@ parse_dst_operand(
dst->Dimension.Indirect = 0;
dst->Dimension.Dimension = 0;
dst->Dimension.Index = bracket[0].index;
if (bracket[0].ind_file != TGSI_FILE_NULL) {
dst->Dimension.Indirect = 1;
dst->DimIndirect.File = bracket[0].ind_file;
dst->DimIndirect.Index = bracket[0].ind_index;
dst->DimIndirect.Swizzle = bracket[0].ind_comp;
dst->DimIndirect.ArrayID = bracket[0].ind_array;
}
bracket[0] = bracket[1];
}
dst->Register.Index = bracket[0].index;
@ -1623,6 +1638,10 @@ static boolean translate( struct translate_ctx *ctx )
if (!parse_header( ctx ))
return FALSE;
if (ctx->processor == TGSI_PROCESSOR_TESS_CTRL ||
ctx->processor == TGSI_PROCESSOR_TESS_EVAL)
ctx->implied_array_size = 32;
while (*ctx->cur != '\0') {
uint label_val = 0;
if (!eat_white( &ctx->cur )) {

54
src/gallium/auxiliary/util/u_blitter.c
View file

@ -104,7 +104,7 @@ struct blitter_context_priv
void *fs_resolve_uint[PIPE_MAX_TEXTURE_TYPES][NUM_RESOLVE_FRAG_SHADERS][2];
/* Blend state. */
void *blend[PIPE_MASK_RGBA+1]; /**< blend state with writemask */
void *blend[PIPE_MASK_RGBA+1][2]; /**< blend state with writemask */
void *blend_clear[GET_CLEAR_BLEND_STATE_IDX(PIPE_CLEAR_COLOR)+1];
/* Depth stencil alpha state. */
@ -159,7 +159,7 @@ struct blitter_context *util_blitter_create(struct pipe_context *pipe)
struct pipe_rasterizer_state rs_state;
struct pipe_sampler_state sampler_state;
struct pipe_vertex_element velem[2];
unsigned i;
unsigned i, j;
ctx = CALLOC_STRUCT(blitter_context_priv);
if (!ctx)
@ -208,8 +208,20 @@ struct blitter_context *util_blitter_create(struct pipe_context *pipe)
memset(&blend, 0, sizeof(blend));
for (i = 0; i <= PIPE_MASK_RGBA; i++) {
blend.rt[0].colormask = i;
ctx->blend[i] = pipe->create_blend_state(pipe, &blend);
for (j = 0; j < 2; j++) {
memset(&blend.rt[0], 0, sizeof(blend.rt[0]));
blend.rt[0].colormask = i;
if (j) {
blend.rt[0].blend_enable = 1;
blend.rt[0].rgb_func = PIPE_BLEND_ADD;
blend.rt[0].rgb_src_factor = PIPE_BLENDFACTOR_SRC_ALPHA;
blend.rt[0].rgb_dst_factor = PIPE_BLENDFACTOR_INV_SRC_ALPHA;
blend.rt[0].alpha_func = PIPE_BLEND_ADD;
blend.rt[0].alpha_src_factor = PIPE_BLENDFACTOR_SRC_ALPHA;
blend.rt[0].alpha_dst_factor = PIPE_BLENDFACTOR_INV_SRC_ALPHA;
}
ctx->blend[i][j] = pipe->create_blend_state(pipe, &blend);
}
}
/* depth stencil alpha state objects */
@ -409,9 +421,10 @@ void util_blitter_destroy(struct blitter_context *blitter)
struct pipe_context *pipe = blitter->pipe;
int i, j, f;
for (i = 0; i <= PIPE_MASK_RGBA; i++) {
pipe->delete_blend_state(pipe, ctx->blend[i]);
}
for (i = 0; i <= PIPE_MASK_RGBA; i++)
for (j = 0; j < 2; j++)
pipe->delete_blend_state(pipe, ctx->blend[i][j]);
for (i = 0; i < Elements(ctx->blend_clear); i++) {
if (ctx->blend_clear[i])
pipe->delete_blend_state(pipe, ctx->blend_clear[i]);
@ -1217,7 +1230,7 @@ static void *get_clear_blend_state(struct blitter_context_priv *ctx,
/* Return an existing blend state. */
if (!clear_buffers)
return ctx->blend[0];
return ctx->blend[0][0];
index = GET_CLEAR_BLEND_STATE_IDX(clear_buffers);
@ -1483,7 +1496,8 @@ void util_blitter_copy_texture(struct blitter_context *blitter,
/* Copy. */
util_blitter_blit_generic(blitter, dst_view, &dstbox,
src_view, srcbox, src->width0, src->height0,
PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL);
PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
FALSE);
pipe_surface_reference(&dst_view, NULL);
pipe_sampler_view_reference(&src_view, NULL);
@ -1496,7 +1510,8 @@ void util_blitter_blit_generic(struct blitter_context *blitter,
const struct pipe_box *srcbox,
unsigned src_width0, unsigned src_height0,
unsigned mask, unsigned filter,
const struct pipe_scissor_state *scissor)
const struct pipe_scissor_state *scissor,
boolean alpha_blend)
{
struct blitter_context_priv *ctx = (struct blitter_context_priv*)blitter;
struct pipe_context *pipe = ctx->base.pipe;
@ -1550,7 +1565,7 @@ void util_blitter_blit_generic(struct blitter_context *blitter,
fb_state.zsbuf = NULL;
if (blit_depth || blit_stencil) {
pipe->bind_blend_state(pipe, ctx->blend[0]);
pipe->bind_blend_state(pipe, ctx->blend[0][0]);
if (blit_depth && blit_stencil) {
pipe->bind_depth_stencil_alpha_state(pipe,
@ -1573,7 +1588,9 @@ void util_blitter_blit_generic(struct blitter_context *blitter,
}
} else {
pipe->bind_blend_state(pipe, ctx->blend[mask & PIPE_MASK_RGBA]);
unsigned colormask = mask & PIPE_MASK_RGBA;
pipe->bind_blend_state(pipe, ctx->blend[colormask][alpha_blend]);
pipe->bind_depth_stencil_alpha_state(pipe, ctx->dsa_keep_depth_stencil);
ctx->bind_fs_state(pipe,
blitter_get_fs_texfetch_col(ctx, src->format, src_target,
@ -1786,7 +1803,8 @@ util_blitter_blit(struct blitter_context *blitter,
util_blitter_blit_generic(blitter, dst_view, &info->dst.box,
src_view, &info->src.box, src->width0, src->height0,
info->mask, info->filter,
info->scissor_enable ? &info->scissor : NULL);
info->scissor_enable ? &info->scissor : NULL,
info->alpha_blend);
pipe_surface_reference(&dst_view, NULL);
pipe_sampler_view_reference(&src_view, NULL);
@ -1815,7 +1833,7 @@ void util_blitter_clear_render_target(struct blitter_context *blitter,
blitter_disable_render_cond(ctx);
/* bind states */
pipe->bind_blend_state(pipe, ctx->blend[PIPE_MASK_RGBA]);
pipe->bind_blend_state(pipe, ctx->blend[PIPE_MASK_RGBA][0]);
pipe->bind_depth_stencil_alpha_state(pipe, ctx->dsa_keep_depth_stencil);
bind_fs_write_one_cbuf(ctx);
pipe->bind_vertex_elements_state(pipe, ctx->velem_state);
@ -1867,7 +1885,7 @@ void util_blitter_clear_depth_stencil(struct blitter_context *blitter,
blitter_disable_render_cond(ctx);
/* bind states */
pipe->bind_blend_state(pipe, ctx->blend[0]);
pipe->bind_blend_state(pipe, ctx->blend[0][0]);
if ((clear_flags & PIPE_CLEAR_DEPTHSTENCIL) == PIPE_CLEAR_DEPTHSTENCIL) {
sr.ref_value[0] = stencil & 0xff;
pipe->bind_depth_stencil_alpha_state(pipe, ctx->dsa_write_depth_stencil);
@ -1933,8 +1951,8 @@ void util_blitter_custom_depth_stencil(struct blitter_context *blitter,
blitter_disable_render_cond(ctx);
/* bind states */
pipe->bind_blend_state(pipe, cbsurf ? ctx->blend[PIPE_MASK_RGBA] :
ctx->blend[0]);
pipe->bind_blend_state(pipe, cbsurf ? ctx->blend[PIPE_MASK_RGBA][0] :
ctx->blend[0][0]);
pipe->bind_depth_stencil_alpha_state(pipe, dsa_stage);
if (cbsurf)
bind_fs_write_one_cbuf(ctx);
@ -2187,7 +2205,7 @@ void util_blitter_custom_color(struct blitter_context *blitter,
/* bind states */
pipe->bind_blend_state(pipe, custom_blend ? custom_blend
: ctx->blend[PIPE_MASK_RGBA]);
: ctx->blend[PIPE_MASK_RGBA][0]);
pipe->bind_depth_stencil_alpha_state(pipe, ctx->dsa_keep_depth_stencil);
bind_fs_write_one_cbuf(ctx);
pipe->bind_vertex_elements_state(pipe, ctx->velem_state);

3
src/gallium/auxiliary/util/u_blitter.h
View file

@ -246,7 +246,8 @@ void util_blitter_blit_generic(struct blitter_context *blitter,
const struct pipe_box *srcbox,
unsigned src_width0, unsigned src_height0,
unsigned mask, unsigned filter,
const struct pipe_scissor_state *scissor);
const struct pipe_scissor_state *scissor,
boolean alpha_blend);
void util_blitter_blit(struct blitter_context *blitter,
const struct pipe_blit_info *info);

3
src/gallium/auxiliary/util/u_surface.c
View file

@ -676,6 +676,9 @@ util_try_blit_via_copy_region(struct pipe_context *ctx,
return FALSE;
}
if (blit->alpha_blend)
return FALSE;
ctx->resource_copy_region(ctx, blit->dst.resource, blit->dst.level,
blit->dst.box.x, blit->dst.box.y, blit->dst.box.z,
blit->src.resource, blit->src.level,

4
src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
View file

@ -13,8 +13,8 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63728 bytes, from 2015-08-05 18:07:28)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67120 bytes, from 2015-08-14 23:22:03)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63915 bytes, from 2015-08-24 16:56:28)
Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)

23
src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
View file

@ -13,8 +13,8 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63728 bytes, from 2015-08-05 18:07:28)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67120 bytes, from 2015-08-14 23:22:03)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63915 bytes, from 2015-08-24 16:56:28)
Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
@ -326,6 +326,13 @@ enum a3xx_tex_type {
A3XX_TEX_3D = 3,
};
enum a3xx_tex_msaa {
A3XX_TPL1_MSAA1X = 0,
A3XX_TPL1_MSAA2X = 1,
A3XX_TPL1_MSAA4X = 2,
A3XX_TPL1_MSAA8X = 3,
};
#define A3XX_INT0_RBBM_GPU_IDLE 0x00000001
#define A3XX_INT0_RBBM_AHB_ERROR 0x00000002
#define A3XX_INT0_RBBM_REG_TIMEOUT 0x00000004
@ -2652,6 +2659,7 @@ static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val)
#define REG_A3XX_VGT_IMMED_DATA 0x000021fd
#define REG_A3XX_TEX_SAMP_0 0x00000000
#define A3XX_TEX_SAMP_0_CLAMPENABLE 0x00000001
#define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002
#define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c
#define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2
@ -2695,6 +2703,7 @@ static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val
{
return ((val) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK;
}
#define A3XX_TEX_SAMP_0_CUBEMAPSEAMLESSFILTOFF 0x01000000
#define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000
#define REG_A3XX_TEX_SAMP_1 0x00000001
@ -2750,6 +2759,12 @@ static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val)
{
return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK;
}
#define A3XX_TEX_CONST_0_MSAATEX__MASK 0x00300000
#define A3XX_TEX_CONST_0_MSAATEX__SHIFT 20
static inline uint32_t A3XX_TEX_CONST_0_MSAATEX(enum a3xx_tex_msaa val)
{
return ((val) << A3XX_TEX_CONST_0_MSAATEX__SHIFT) & A3XX_TEX_CONST_0_MSAATEX__MASK;
}
#define A3XX_TEX_CONST_0_FMT__MASK 0x1fc00000
#define A3XX_TEX_CONST_0_FMT__SHIFT 22
static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val)
@ -2785,7 +2800,7 @@ static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val)
}
#define REG_A3XX_TEX_CONST_2 0x00000002
#define A3XX_TEX_CONST_2_INDX__MASK 0x000000ff
#define A3XX_TEX_CONST_2_INDX__MASK 0x000001ff
#define A3XX_TEX_CONST_2_INDX__SHIFT 0
static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val)
{
@ -2805,7 +2820,7 @@ static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
}
#define REG_A3XX_TEX_CONST_3 0x00000003
#define A3XX_TEX_CONST_3_LAYERSZ1__MASK 0x00007fff
#define A3XX_TEX_CONST_3_LAYERSZ1__MASK 0x0001ffff
#define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT 0
static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val)
{

11
src/gallium/drivers/freedreno/a3xx/fd3_format.c
View file

@ -262,6 +262,15 @@ static struct fd3_format formats[PIPE_FORMAT_COUNT] = {
_T(ETC2_R11_SNORM, ETC2_R11_SNORM, NONE, WZYX),
_T(ETC2_RG11_UNORM, ETC2_RG11_UNORM, NONE, WZYX),
_T(ETC2_RG11_SNORM, ETC2_RG11_SNORM, NONE, WZYX),
_T(DXT1_RGB, DXT1, NONE, WZYX),
_T(DXT1_SRGB, DXT1, NONE, WZYX),
_T(DXT1_RGBA, DXT1, NONE, WZYX),
_T(DXT1_SRGBA, DXT1, NONE, WZYX),
_T(DXT3_RGBA, DXT3, NONE, WZYX),
_T(DXT3_SRGBA, DXT3, NONE, WZYX),
_T(DXT5_RGBA, DXT5, NONE, WZYX),
_T(DXT5_SRGBA, DXT5, NONE, WZYX),
};
enum a3xx_vtx_fmt
@ -301,7 +310,7 @@ fd3_pipe2fetchsize(enum pipe_format format)
{
if (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
format = PIPE_FORMAT_Z32_FLOAT;
switch (util_format_get_blocksizebits(format)) {
switch (util_format_get_blocksizebits(format) / util_format_get_blockwidth(format)) {
case 8: return TFETCH_1_BYTE;
case 16: return TFETCH_2_BYTE;
case 32: return TFETCH_4_BYTE;

2
src/gallium/drivers/freedreno/a3xx/fd3_rasterizer.c
View file

@ -73,7 +73,7 @@ fd3_rasterizer_state_create(struct pipe_context *pctx,
so->gras_su_poly_offset_scale =
A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(cso->offset_scale);
so->gras_su_poly_offset_offset =
A3XX_GRAS_SU_POLY_OFFSET_OFFSET(cso->offset_units);
A3XX_GRAS_SU_POLY_OFFSET_OFFSET(cso->offset_units * 2.0f);
so->gras_su_mode_control =
A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(cso->line_width/2.0);

3
src/gallium/drivers/freedreno/a3xx/fd3_texture.c
View file

@ -115,6 +115,7 @@ fd3_sampler_state_create(struct pipe_context *pctx,
so->texsamp0 =
COND(!cso->normalized_coords, A3XX_TEX_SAMP_0_UNNORM_COORDS) |
COND(!cso->seamless_cube_map, A3XX_TEX_SAMP_0_CUBEMAPSEAMLESSFILTOFF) |
COND(miplinear, A3XX_TEX_SAMP_0_MIPFILTER_LINEAR) |
A3XX_TEX_SAMP_0_XY_MAG(tex_filter(cso->mag_img_filter, aniso)) |
A3XX_TEX_SAMP_0_XY_MIN(tex_filter(cso->min_img_filter, aniso)) |
@ -239,7 +240,7 @@ fd3_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
A3XX_TEX_CONST_1_HEIGHT(u_minify(prsc->height0, lvl));
/* when emitted, A3XX_TEX_CONST_2_INDX() must be OR'd in: */
so->texconst2 =
A3XX_TEX_CONST_2_PITCH(rsc->slices[lvl].pitch * rsc->cpp);
A3XX_TEX_CONST_2_PITCH(util_format_get_nblocksx(cso->format, rsc->slices[lvl].pitch) * rsc->cpp);
switch (prsc->target) {
case PIPE_TEXTURE_1D_ARRAY:
case PIPE_TEXTURE_2D_ARRAY:

12
src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
View file

@ -13,8 +13,8 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63728 bytes, from 2015-08-05 18:07:28)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67120 bytes, from 2015-08-14 23:22:03)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63915 bytes, from 2015-08-24 16:56:28)
Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
@ -162,10 +162,13 @@ enum a4xx_tex_fmt {
TFMT4_8_UNORM = 4,
TFMT4_8_8_UNORM = 14,
TFMT4_8_8_8_8_UNORM = 28,
TFMT4_8_SNORM = 5,
TFMT4_8_8_SNORM = 15,
TFMT4_8_8_8_8_SNORM = 29,
TFMT4_8_UINT = 6,
TFMT4_8_8_UINT = 16,
TFMT4_8_8_8_8_UINT = 30,
TFMT4_8_SINT = 7,
TFMT4_8_8_SINT = 17,
TFMT4_8_8_8_8_SINT = 31,
TFMT4_16_UINT = 21,
@ -430,7 +433,7 @@ static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
}
#define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000
#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0x007fc000
#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000
#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14
static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
{
@ -440,7 +443,7 @@ static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; }
static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; }
#define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x0001fff8
#define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8
#define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3
static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val)
{
@ -1460,6 +1463,7 @@ static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)
{
return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK;
}
#define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000
#define REG_A4XX_SP_CS_CTRL_REG0 0x00002300

1
src/gallium/drivers/freedreno/a4xx/fd4_emit.h
View file

@ -56,6 +56,7 @@ struct fd4_emit {
uint32_t sprite_coord_enable; /* bitmask */
bool sprite_coord_mode;
bool rasterflat;
bool no_decode_srgb;
/* cached to avoid repeated lookups of same variants: */
struct ir3_shader_variant *vp, *fp;

10
src/gallium/drivers/freedreno/a4xx/fd4_format.c
View file

@ -79,9 +79,9 @@ struct fd4_format {
static struct fd4_format formats[PIPE_FORMAT_COUNT] = {
/* 8-bit */
VT(R8_UNORM, 8_UNORM, R8_UNORM, WZYX),
V_(R8_SNORM, 8_SNORM, NONE, WZYX),
V_(R8_UINT, 8_UINT, NONE, WZYX),
V_(R8_SINT, 8_SINT, NONE, WZYX),
VT(R8_SNORM, 8_SNORM, NONE, WZYX),
VT(R8_UINT, 8_UINT, NONE, WZYX),
VT(R8_SINT, 8_SINT, NONE, WZYX),
V_(R8_USCALED, 8_UINT, NONE, WZYX),
V_(R8_SSCALED, 8_UINT, NONE, WZYX),
@ -115,8 +115,8 @@ static struct fd4_format formats[PIPE_FORMAT_COUNT] = {
VT(R8G8_UNORM, 8_8_UNORM, R8G8_UNORM, WZYX),
VT(R8G8_SNORM, 8_8_SNORM, R8G8_SNORM, WZYX),
VT(R8G8_UINT, 8_8_UINT, NONE, WZYX),
VT(R8G8_SINT, 8_8_SINT, NONE, WZYX),
VT(R8G8_UINT, 8_8_UINT, R8G8_UINT, WZYX),
VT(R8G8_SINT, 8_8_SINT, R8G8_SINT, WZYX),
V_(R8G8_USCALED, 8_8_UINT, NONE, WZYX),
V_(R8G8_SSCALED, 8_8_SINT, NONE, WZYX),

22
src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
View file

@ -46,7 +46,8 @@
static void
emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
struct pipe_surface **bufs, uint32_t *bases, uint32_t bin_w)
struct pipe_surface **bufs, uint32_t *bases,
uint32_t bin_w, bool decode_srgb)
{
enum a4xx_tile_mode tile_mode;
unsigned i;
@ -60,6 +61,7 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
enum a4xx_color_fmt format = 0;
enum a3xx_color_swap swap = WZYX;
bool srgb = false;
struct fd_resource *rsc = NULL;
struct fd_resource_slice *slice = NULL;
uint32_t stride = 0;
@ -68,10 +70,9 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
if ((i < nr_bufs) && bufs[i]) {
struct pipe_surface *psurf = bufs[i];
enum pipe_format pformat = 0;
enum pipe_format pformat = psurf->format;
rsc = fd_resource(psurf->texture);
pformat = psurf->format;
/* In case we're drawing to Z32F_S8, the "color" actually goes to
* the stencil
@ -86,6 +87,11 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
format = fd4_pipe2color(pformat);
swap = fd4_pipe2swap(pformat);
if (decode_srgb)
srgb = util_format_is_srgb(pformat);
else
pformat = util_format_linear(pformat);
debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
offset = fd_resource_offset(rsc, psurf->u.tex.level,
@ -108,7 +114,8 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
OUT_RING(ring, A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap));
A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
COND(srgb, A4XX_RB_MRT_BUF_INFO_COLOR_SRGB));
if (bin_w || (i >= nr_bufs) || !bufs[i]) {
OUT_RING(ring, base);
OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(stride));
@ -282,7 +289,7 @@ emit_mem2gmem_surf(struct fd_context *ctx, uint32_t *bases,
struct fd_ringbuffer *ring = ctx->ring;
struct pipe_surface *zsbufs[2];
emit_mrt(ring, nr_bufs, bufs, bases, bin_w);
emit_mrt(ring, nr_bufs, bufs, bases, bin_w, false);
if (bufs[0] && (bufs[0]->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)) {
/* The gmem_restore_tex logic will put the first buffer's stencil
@ -315,6 +322,7 @@ fd4_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
.key = {
.half_precision = fd_half_precision(pfb),
},
.no_decode_srgb = true,
};
unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
float x0, y0, x1, y1;
@ -520,7 +528,7 @@ fd4_emit_sysmem_prep(struct fd_context *ctx)
OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0);
emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0, true);
/* setup scissor/offset for current tile: */
OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
@ -677,7 +685,7 @@ fd4_emit_tile_renderprep(struct fd_context *ctx, struct fd_tile *tile)
OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem->cbuf_base, gmem->bin_w);
emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem->cbuf_base, gmem->bin_w, true);
/* setup scissor/offset for current tile: */
OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);

7
src/gallium/drivers/freedreno/a4xx/fd4_program.c
View file

@ -450,10 +450,15 @@ fd4_program_emit(struct fd_ringbuffer *ring, struct fd4_emit *emit,
OUT_PKT0(ring, REG_A4XX_SP_FS_MRT_REG(0), 8);
for (i = 0; i < 8; i++) {
enum a4xx_color_fmt format = 0;
if (i < nr)
bool srgb = false;
if (i < nr) {
format = fd4_emit_format(bufs[i]);
if (bufs[i] && !emit->no_decode_srgb)
srgb = util_format_is_srgb(bufs[i]->format);
}
OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
A4XX_SP_FS_MRT_REG_MRTFORMAT(format) |
COND(srgb, A4XX_SP_FS_MRT_REG_COLOR_SRGB) |
COND(emit->key.half_precision,
A4XX_SP_FS_MRT_REG_HALF_PRECISION));
}

4
src/gallium/drivers/freedreno/a4xx/fd4_texture.c
View file

@ -187,9 +187,9 @@ fd4_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
A4XX_TEX_CONST_3_LAYERSZ(rsc->layer_size);
break;
case PIPE_TEXTURE_CUBE:
case PIPE_TEXTURE_CUBE_ARRAY: /* ?? not sure about _CUBE_ARRAY */
case PIPE_TEXTURE_CUBE_ARRAY:
so->texconst3 =
A4XX_TEX_CONST_3_DEPTH(1) |
A4XX_TEX_CONST_3_DEPTH(prsc->array_size / 6) |
A4XX_TEX_CONST_3_LAYERSZ(rsc->layer_size);
break;
case PIPE_TEXTURE_3D:

4
src/gallium/drivers/freedreno/adreno_common.xml.h
View file

@ -13,8 +13,8 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63728 bytes, from 2015-08-05 18:07:28)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67120 bytes, from 2015-08-14 23:22:03)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63915 bytes, from 2015-08-24 16:56:28)
Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)

4
src/gallium/drivers/freedreno/adreno_pm4.xml.h
View file

@ -13,8 +13,8 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63728 bytes, from 2015-08-05 18:07:28)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67120 bytes, from 2015-08-14 23:22:03)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63915 bytes, from 2015-08-24 16:56:28)
Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)

4
src/gallium/drivers/freedreno/freedreno_context.c
View file

@ -131,11 +131,13 @@ static void
fd_context_flush(struct pipe_context *pctx, struct pipe_fence_handle **fence,
unsigned flags)
{
struct fd_ringbuffer *ring = fd_context(pctx)->ring;
fd_context_render(pctx);
if (fence) {
fd_screen_fence_ref(pctx->screen, fence, NULL);
*fence = fd_fence_create(pctx);
*fence = fd_fence_create(pctx, fd_ringbuffer_timestamp(ring));
}
}

25
src/gallium/drivers/freedreno/freedreno_fence.c
View file

@ -50,35 +50,18 @@ fd_screen_fence_ref(struct pipe_screen *pscreen,
*ptr = pfence;
}
/* TODO we need to spiff out libdrm_freedreno a bit to allow passing
* the timeout.. and maybe a better way to check if fence has been
* signaled. The current implementation is a bit lame for now to
* avoid bumping libdrm version requirement.
*/
boolean fd_screen_fence_signalled(struct pipe_screen *screen,
struct pipe_fence_handle *fence)
{
uint32_t timestamp = fd_ringbuffer_timestamp(fence->ctx->ring);
/* TODO util helper for compare w/ rollover? */
return timestamp >= fence->timestamp;
}
boolean fd_screen_fence_finish(struct pipe_screen *screen,
struct pipe_fence_handle *fence,
uint64_t timeout)
{
if (!timeout)
return fd_screen_fence_signalled(screen, fence);
if (fd_pipe_wait(fence->screen->pipe, fence->timestamp))
if (fd_pipe_wait_timeout(fence->screen->pipe, fence->timestamp, timeout))
return false;
return true;
}
struct pipe_fence_handle * fd_fence_create(struct pipe_context *pctx)
struct pipe_fence_handle * fd_fence_create(struct pipe_context *pctx,
uint32_t timestamp)
{
struct pipe_fence_handle *fence;
struct fd_context *ctx = fd_context(pctx);
@ -91,7 +74,7 @@ struct pipe_fence_handle * fd_fence_create(struct pipe_context *pctx)
fence->ctx = ctx;
fence->screen = ctx->screen;
fence->timestamp = fd_ringbuffer_timestamp(ctx->ring);
fence->timestamp = timestamp;
return fence;
}

5
src/gallium/drivers/freedreno/freedreno_fence.h
View file

@ -34,11 +34,10 @@
void fd_screen_fence_ref(struct pipe_screen *pscreen,
struct pipe_fence_handle **ptr,
struct pipe_fence_handle *pfence);
boolean fd_screen_fence_signalled(struct pipe_screen *screen,
struct pipe_fence_handle *pfence);
boolean fd_screen_fence_finish(struct pipe_screen *screen,
struct pipe_fence_handle *pfence,
uint64_t timeout);
struct pipe_fence_handle * fd_fence_create(struct pipe_context *pctx);
struct pipe_fence_handle * fd_fence_create(struct pipe_context *pctx,
uint32_t timestamp);
#endif /* FREEDRENO_FENCE_H_ */

9
src/gallium/drivers/freedreno/freedreno_resource.c
View file

@ -222,7 +222,7 @@ fd_resource_transfer_map(struct pipe_context *pctx,
ptrans->level = level;
ptrans->usage = usage;
ptrans->box = *box;
ptrans->stride = slice->pitch * rsc->cpp;
ptrans->stride = util_format_get_nblocksx(format, slice->pitch) * rsc->cpp;
ptrans->layer_stride = slice->size0;
if (usage & PIPE_TRANSFER_READ)
@ -375,9 +375,11 @@ setup_slices(struct fd_resource *rsc, uint32_t alignment)
for (level = 0; level <= prsc->last_level; level++) {
struct fd_resource_slice *slice = fd_resource_slice(rsc, level);
uint32_t blocks;
slice->pitch = width = align(width, 32);
slice->offset = size;
blocks = util_format_get_nblocks(prsc->format, width, height);
/* 1d array and 2d array textures must all have the same layer size
* for each miplevel on a3xx. 3d textures can have different layer
* sizes for high levels, but the hw auto-sizer is buggy (or at least
@ -387,9 +389,9 @@ setup_slices(struct fd_resource *rsc, uint32_t alignment)
if (prsc->target == PIPE_TEXTURE_3D && (
level == 1 ||
(level > 1 && rsc->slices[level - 1].size0 > 0xf000)))
slice->size0 = align(slice->pitch * height * rsc->cpp, alignment);
slice->size0 = align(blocks * rsc->cpp, alignment);
else if (level == 0 || rsc->layer_first || alignment == 1)
slice->size0 = align(slice->pitch * height * rsc->cpp, alignment);
slice->size0 = align(blocks * rsc->cpp, alignment);
else
slice->size0 = rsc->slices[level - 1].size0;
@ -459,7 +461,6 @@ fd_resource_create(struct pipe_screen *pscreen,
if (is_a4xx(fd_screen(pscreen))) {
switch (tmpl->target) {
case PIPE_TEXTURE_3D:
/* TODO 3D_ARRAY? */
rsc->layer_first = false;
break;
default:

10
src/gallium/drivers/freedreno/freedreno_screen.c
View file

@ -163,7 +163,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_TEXTURE_MULTISAMPLE:
case PIPE_CAP_TEXTURE_BARRIER:
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
case PIPE_CAP_CUBE_MAP_ARRAY:
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
case PIPE_CAP_START_INSTANCE:
case PIPE_CAP_COMPUTE:
@ -176,6 +175,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_INDEP_BLEND_ENABLE:
case PIPE_CAP_INDEP_BLEND_FUNC:
case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
return is_a3xx(screen) || is_a4xx(screen);
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
@ -191,8 +191,13 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return 16383;
case PIPE_CAP_DEPTH_CLIP_DISABLE:
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
return is_a3xx(screen);
case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
case PIPE_CAP_CUBE_MAP_ARRAY:
return is_a4xx(screen);
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
return 256;
@ -202,7 +207,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return is_ir3(screen) ? 130 : 120;
/* Unsupported features. */
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
@ -230,8 +234,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
case PIPE_CAP_DEPTH_BOUNDS_TEST:
return 0;

13
src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
View file

@ -1636,6 +1636,11 @@ emit_tex(struct ir3_compile *ctx, nir_tex_instr *tex)
coord[i] = ir3_SHL_B(b, coord[i], 0, lod, 0);
}
/* the array coord for cube arrays needs 0.5 added to it */
if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE && tex->is_array &&
opc != OPC_ISAML)
coord[3] = ir3_ADD_F(b, coord[3], 0, create_immed(b, fui(0.5)), 0);
/*
* lay out the first argument in the proper order:
* - actual coordinates first
@ -1759,6 +1764,12 @@ emit_tex_txs(struct ir3_compile *ctx, nir_tex_instr *tex)
tex_info(tex, &flags, &coords);
/* Actually we want the number of dimensions, not coordinates. This
* distinction only matters for cubes.
*/
if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
coords = 2;
dst = get_dst(ctx, &tex->dest, 4);
compile_assert(ctx, tex->num_srcs == 1);
@ -2301,7 +2312,7 @@ emit_instructions(struct ir3_compile *ctx)
ctx->ir = ir3_create(ctx->compiler, ninputs, noutputs);
/* Create inputs in first block: */
ctx->block = get_block(ctx, fxn->start_block);
ctx->block = get_block(ctx, nir_start_block(fxn));
ctx->in_block = ctx->block;
list_addtail(&ctx->block->node, &ctx->ir->block_list);

1
src/gallium/drivers/freedreno/ir3/ir3_nir_lower_if_else.c
View file

@ -29,6 +29,7 @@
#include "ir3_nir.h"
#include "glsl/nir/nir_builder.h"
#include "glsl/nir/nir_control_flow.h"
/* Based on nir_opt_peephole_select, and hacked up to more aggressively
* flatten anything that can be flattened

2
src/gallium/drivers/freedreno/ir3/ir3_ra.c
View file

@ -189,7 +189,7 @@ ir3_ra_alloc_reg_set(void *memctx)
}
/* allocate the reg-set.. */
set->regs = ra_alloc_reg_set(set, ra_reg_count);
set->regs = ra_alloc_reg_set(set, ra_reg_count, true);
set->ra_reg_to_gpr = ralloc_array(set, uint16_t, ra_reg_count);
set->gpr_to_ra_reg = ralloc_array(set, uint16_t *, total_class_count);

3
src/gallium/drivers/i915/i915_surface.c
View file

@ -120,7 +120,8 @@ i915_surface_copy_render(struct pipe_context *pipe,
util_blitter_blit_generic(i915->blitter, dst_view, &dstbox,
src_view, src_box, src_width0, src_height0,
PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL);
PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
FALSE);
return;
fallback:

3
src/gallium/drivers/nouveau/Makefile.sources
View file

@ -121,7 +121,8 @@ NV50_CODEGEN_SOURCES := \
codegen/nv50_ir_target_nv50.cpp \
codegen/nv50_ir_target_nv50.h \
codegen/nv50_ir_util.cpp \
codegen/nv50_ir_util.h
codegen/nv50_ir_util.h \
codegen/unordered_set.h
NVC0_CODEGEN_SOURCES := \
codegen/nv50_ir_emit_gk110.cpp \

8
src/gallium/drivers/nouveau/codegen/nv50_ir.h
View file

@ -29,8 +29,8 @@
#include <deque>
#include <list>
#include <vector>
#include <tr1/unordered_set>
#include "codegen/unordered_set.h"
#include "codegen/nv50_ir_util.h"
#include "codegen/nv50_ir_graph.h"
@ -585,10 +585,10 @@ public:
static inline Value *get(Iterator&);
std::tr1::unordered_set<ValueRef *> uses;
unordered_set<ValueRef *> uses;
std::list<ValueDef *> defs;
typedef std::tr1::unordered_set<ValueRef *>::iterator UseIterator;
typedef std::tr1::unordered_set<ValueRef *>::const_iterator UseCIterator;
typedef unordered_set<ValueRef *>::iterator UseIterator;
typedef unordered_set<ValueRef *>::const_iterator UseCIterator;
typedef std::list<ValueDef *>::iterator DefIterator;
typedef std::list<ValueDef *>::const_iterator DefCIterator;

1
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
View file

@ -933,6 +933,7 @@ CodeEmitterGK110::emitCVT(const Instruction *i)
code[0] |= typeSizeofLog2(dType) << 10;
code[0] |= typeSizeofLog2(i->sType) << 12;
code[1] |= i->subOp << 12;
if (isSignedIntType(dType))
code[0] |= 0x4000;

2
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
View file

@ -818,6 +818,7 @@ CodeEmitterGM107::emitI2F()
emitField(0x31, 1, (insn->op == OP_ABS) || insn->src(0).mod.abs());
emitCC (0x2f);
emitField(0x2d, 1, (insn->op == OP_NEG) || insn->src(0).mod.neg());
emitField(0x29, 2, insn->subOp);
emitRND (0x27, rnd, -1);
emitField(0x0d, 1, isSignedType(insn->sType));
emitField(0x0a, 2, util_logbase2(typeSizeof(insn->sType)));
@ -850,6 +851,7 @@ CodeEmitterGM107::emitI2I()
emitField(0x31, 1, (insn->op == OP_ABS) || insn->src(0).mod.abs());
emitCC (0x2f);
emitField(0x2d, 1, (insn->op == OP_NEG) || insn->src(0).mod.neg());
emitField(0x29, 2, insn->subOp);
emitField(0x0d, 1, isSignedType(insn->sType));
emitField(0x0c, 1, isSignedType(insn->dType));
emitField(0x0a, 2, util_logbase2(typeSizeof(insn->sType)));

21
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
View file

@ -1020,6 +1020,10 @@ CodeEmitterNVC0::emitCVT(Instruction *i)
code[0] |= util_logbase2(typeSizeof(dType)) << 20;
code[0] |= util_logbase2(typeSizeof(i->sType)) << 23;
// for 8/16 source types, the byte/word is in subOp. word 1 is
// represented as 2.
code[1] |= i->subOp << 0x17;
if (sat)
code[0] |= 0x20;
if (abs)
@ -2614,11 +2618,12 @@ private:
int imul; // integer MUL to MUL delay 3
} res;
struct ScoreData {
int r[64];
int r[256];
int p[8];
int c;
} rd, wr;
int base;
int regs;
void rebase(const int base)
{
@ -2627,7 +2632,7 @@ private:
return;
this->base = 0;
for (int i = 0; i < 64; ++i) {
for (int i = 0; i < regs; ++i) {
rd.r[i] += delta;
wr.r[i] += delta;
}
@ -2646,16 +2651,17 @@ private:
res.imul += delta;
res.tex += delta;
}
void wipe()
void wipe(int regs)
{
memset(&rd, 0, sizeof(rd));
memset(&wr, 0, sizeof(wr));
memset(&res, 0, sizeof(res));
this->regs = regs;
}
int getLatest(const ScoreData& d) const
{
int max = 0;
for (int i = 0; i < 64; ++i)
for (int i = 0; i < regs; ++i)
if (d.r[i] > max)
max = d.r[i];
for (int i = 0; i < 8; ++i)
@ -2690,7 +2696,7 @@ private:
}
void setMax(const RegScores *that)
{
for (int i = 0; i < 64; ++i) {
for (int i = 0; i < regs; ++i) {
rd.r[i] = MAX2(rd.r[i], that->rd.r[i]);
wr.r[i] = MAX2(wr.r[i], that->wr.r[i]);
}
@ -2711,7 +2717,7 @@ private:
}
void print(int cycle)
{
for (int i = 0; i < 64; ++i) {
for (int i = 0; i < regs; ++i) {
if (rd.r[i] > cycle)
INFO("rd $r%i @ %i\n", i, rd.r[i]);
if (wr.r[i] > cycle)
@ -2806,9 +2812,10 @@ SchedDataCalculator::getCycles(const Instruction *insn, int origDelay) const
bool
SchedDataCalculator::visit(Function *func)
{
int regs = targ->getFileSize(FILE_GPR) + 1;
scoreBoards.resize(func->cfg.getSize());
for (size_t i = 0; i < scoreBoards.size(); ++i)
scoreBoards[i].wipe();
scoreBoards[i].wipe(regs);
return true;
}

12
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
View file

@ -2990,9 +2990,15 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
case TGSI_OPCODE_UBFE:
FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
src0 = fetchSrc(0, c);
src1 = fetchSrc(1, c);
src2 = fetchSrc(2, c);
mkOp3(OP_INSBF, TYPE_U32, src1, src2, mkImm(0x808), src1);
if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE &&
tgsi.getSrc(2).getFile() == TGSI_FILE_IMMEDIATE) {
src1 = loadImm(NULL, tgsi.getSrc(2).getValueU32(c, info) << 8 |
tgsi.getSrc(1).getValueU32(c, info));
} else {
src1 = fetchSrc(1, c);
src2 = fetchSrc(2, c);
mkOp3(OP_INSBF, TYPE_U32, src1, src2, mkImm(0x808), src1);
}
mkOp2(OP_EXTBF, dstTy, dst0[c], src0, src1);
}
break;

90
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
View file

@ -193,100 +193,16 @@ GM107LoweringPass::visit(Instruction *i)
checkPredicate(i);
switch (i->op) {
case OP_TEX:
case OP_TXB:
case OP_TXL:
case OP_TXF:
case OP_TXG:
return handleTEX(i->asTex());
case OP_TXD:
return handleTXD(i->asTex());
case OP_TXLQ:
return handleTXLQ(i->asTex());
case OP_TXQ:
return handleTXQ(i->asTex());
case OP_EX2:
bld.mkOp1(OP_PREEX2, TYPE_F32, i->getDef(0), i->getSrc(0));
i->setSrc(0, i->getDef(0));
break;
case OP_POW:
return handlePOW(i);
case OP_DIV:
return handleDIV(i);
case OP_MOD:
return handleMOD(i);
case OP_SQRT:
return handleSQRT(i);
case OP_EXPORT:
return handleEXPORT(i);
case OP_PFETCH:
return handlePFETCH(i);
case OP_EMIT:
case OP_RESTART:
return handleOUT(i);
case OP_RDSV:
return handleRDSV(i);
case OP_WRSV:
return handleWRSV(i);
case OP_LOAD:
if (i->src(0).getFile() == FILE_SHADER_INPUT) {
if (prog->getType() == Program::TYPE_COMPUTE) {
i->getSrc(0)->reg.file = FILE_MEMORY_CONST;
i->getSrc(0)->reg.fileIndex = 0;
} else
if (prog->getType() == Program::TYPE_GEOMETRY &&
i->src(0).isIndirect(0)) {
// XXX: this assumes vec4 units
Value *ptr = bld.mkOp2v(OP_SHL, TYPE_U32, bld.getSSA(),
i->getIndirect(0, 0), bld.mkImm(4));
i->setIndirect(0, 0, ptr);
i->op = OP_VFETCH;
} else {
i->op = OP_VFETCH;
assert(prog->getType() != Program::TYPE_FRAGMENT); // INTERP
}
} else if (i->src(0).getFile() == FILE_MEMORY_CONST) {
if (i->src(0).isIndirect(1)) {
Value *ptr;
if (i->src(0).isIndirect(0))
ptr = bld.mkOp3v(OP_INSBF, TYPE_U32, bld.getSSA(),
i->getIndirect(0, 1), bld.mkImm(0x1010),
i->getIndirect(0, 0));
else
ptr = bld.mkOp2v(OP_SHL, TYPE_U32, bld.getSSA(),
i->getIndirect(0, 1), bld.mkImm(16));
i->setIndirect(0, 1, NULL);
i->setIndirect(0, 0, ptr);
i->subOp = NV50_IR_SUBOP_LDC_IS;
}
}
break;
case OP_ATOM:
{
const bool cctl = i->src(0).getFile() == FILE_MEMORY_GLOBAL;
handleATOM(i);
handleCasExch(i, cctl);
}
break;
case OP_SULDB:
case OP_SULDP:
case OP_SUSTB:
case OP_SUSTP:
case OP_SUREDB:
case OP_SUREDP:
handleSurfaceOpNVE4(i->asTex());
break;
case OP_DFDX:
case OP_DFDY:
handleDFDX(i);
break;
return handleDFDX(i);
case OP_POPCNT:
handlePOPCNT(i);
break;
return handlePOPCNT(i);
default:
break;
return NVC0LoweringPass::visit(i);
}
return true;
}
} // namespace nv50_ir

4
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
View file

@ -224,7 +224,7 @@ NVC0LegalizePostRA::findFirstUses(
const Instruction *texi,
const Instruction *insn,
std::list<TexUse> &uses,
std::tr1::unordered_set<const Instruction *>& visited)
unordered_set<const Instruction *>& visited)
{
for (int d = 0; insn->defExists(d); ++d) {
Value *v = insn->getDef(d);
@ -323,7 +323,7 @@ NVC0LegalizePostRA::insertTextureBarriers(Function *fn)
if (!uses)
return false;
for (size_t i = 0; i < texes.size(); ++i) {
std::tr1::unordered_set<const Instruction *> visited;
unordered_set<const Instruction *> visited;
findFirstUses(texes[i], texes[i], uses[i], visited);
}

7
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
View file

@ -20,8 +20,6 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <tr1/unordered_set>
#include "codegen/nv50_ir.h"
#include "codegen/nv50_ir_build_util.h"
@ -73,7 +71,7 @@ private:
inline bool insnDominatedBy(const Instruction *, const Instruction *) const;
void findFirstUses(const Instruction *tex, const Instruction *def,
std::list<TexUse>&,
std::tr1::unordered_set<const Instruction *>&);
unordered_set<const Instruction *>&);
void findOverwritingDefs(const Instruction *tex, Instruction *insn,
const BasicBlock *term,
std::list<TexUse>&);
@ -111,10 +109,11 @@ protected:
void checkPredicate(Instruction *);
virtual bool visit(Instruction *);
private:
virtual bool visit(Function *);
virtual bool visit(BasicBlock *);
virtual bool visit(Instruction *);
void readTessCoord(LValue *dst, int c);

253
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
View file

@ -1023,27 +1023,53 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
case OP_AND:
{
CmpInstruction *cmp = i->getSrc(t)->getInsn()->asCmp();
if (!cmp || cmp->op == OP_SLCT || cmp->getDef(0)->refCount() > 1)
return;
if (!prog->getTarget()->isOpSupported(cmp->op, TYPE_F32))
return;
if (imm0.reg.data.f32 != 1.0)
return;
if (i->getSrc(t)->getInsn()->dType != TYPE_U32)
return;
Instruction *src = i->getSrc(t)->getInsn();
ImmediateValue imm1;
if (imm0.reg.data.u32 == 0) {
i->op = OP_MOV;
i->setSrc(0, new_ImmediateValue(prog, 0u));
i->src(0).mod = Modifier(0);
i->setSrc(1, NULL);
} else if (imm0.reg.data.u32 == ~0U) {
i->op = i->src(t).mod.getOp();
if (t) {
i->setSrc(0, i->getSrc(t));
i->src(0).mod = i->src(t).mod;
}
i->setSrc(1, NULL);
} else if (src->asCmp()) {
CmpInstruction *cmp = src->asCmp();
if (!cmp || cmp->op == OP_SLCT || cmp->getDef(0)->refCount() > 1)
return;
if (!prog->getTarget()->isOpSupported(cmp->op, TYPE_F32))
return;
if (imm0.reg.data.f32 != 1.0)
return;
if (cmp->dType != TYPE_U32)
return;
i->getSrc(t)->getInsn()->dType = TYPE_F32;
if (i->src(t).mod != Modifier(0)) {
assert(i->src(t).mod == Modifier(NV50_IR_MOD_NOT));
i->src(t).mod = Modifier(0);
cmp->setCond = inverseCondCode(cmp->setCond);
}
i->op = OP_MOV;
i->setSrc(s, NULL);
if (t) {
i->setSrc(0, i->getSrc(t));
i->setSrc(t, NULL);
cmp->dType = TYPE_F32;
if (i->src(t).mod != Modifier(0)) {
assert(i->src(t).mod == Modifier(NV50_IR_MOD_NOT));
i->src(t).mod = Modifier(0);
cmp->setCond = inverseCondCode(cmp->setCond);
}
i->op = OP_MOV;
i->setSrc(s, NULL);
if (t) {
i->setSrc(0, i->getSrc(t));
i->setSrc(t, NULL);
}
} else if (prog->getTarget()->isOpSupported(OP_EXTBF, TYPE_U32) &&
src->op == OP_SHR &&
src->src(1).getImmediate(imm1) &&
i->src(t).mod == Modifier(0) &&
util_is_power_of_two(imm0.reg.data.u32 + 1)) {
// low byte = offset, high byte = width
uint32_t ext = (util_last_bit(imm0.reg.data.u32) << 8) | imm1.reg.data.u32;
i->op = OP_EXTBF;
i->setSrc(0, src->getSrc(0));
i->setSrc(1, new_ImmediateValue(prog, ext));
}
}
break;
@ -1106,6 +1132,84 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
i->op = OP_MOV;
break;
}
case OP_CVT: {
Storage res;
// TODO: handle 64-bit values properly
if (typeSizeof(i->dType) == 8 || typeSizeof(i->sType) == 8)
return;
// TODO: handle single byte/word extractions
if (i->subOp)
return;
bld.setPosition(i, true); /* make sure bld is init'ed */
#define CASE(type, dst, fmin, fmax, imin, imax, umin, umax) \
case type: \
switch (i->sType) { \
case TYPE_F32: \
res.data.dst = util_iround(i->saturate ? \
CLAMP(imm0.reg.data.f32, fmin, fmax) : \
imm0.reg.data.f32); \
break; \
case TYPE_S32: \
res.data.dst = i->saturate ? \
CLAMP(imm0.reg.data.s32, imin, imax) : \
imm0.reg.data.s32; \
break; \
case TYPE_U32: \
res.data.dst = i->saturate ? \
CLAMP(imm0.reg.data.u32, umin, umax) : \
imm0.reg.data.u32; \
break; \
case TYPE_S16: \
res.data.dst = i->saturate ? \
CLAMP(imm0.reg.data.s16, imin, imax) : \
imm0.reg.data.s16; \
break; \
case TYPE_U16: \
res.data.dst = i->saturate ? \
CLAMP(imm0.reg.data.u16, umin, umax) : \
imm0.reg.data.u16; \
break; \
default: return; \
} \
i->setSrc(0, bld.mkImm(res.data.dst)); \
break
switch(i->dType) {
CASE(TYPE_U16, u16, 0, UINT16_MAX, 0, UINT16_MAX, 0, UINT16_MAX);
CASE(TYPE_S16, s16, INT16_MIN, INT16_MAX, INT16_MIN, INT16_MAX, 0, INT16_MAX);
CASE(TYPE_U32, u32, 0, UINT32_MAX, 0, INT32_MAX, 0, UINT32_MAX);
CASE(TYPE_S32, s32, INT32_MIN, INT32_MAX, INT32_MIN, INT32_MAX, 0, INT32_MAX);
case TYPE_F32:
switch (i->sType) {
case TYPE_F32:
res.data.f32 = i->saturate ?
CLAMP(imm0.reg.data.f32, 0.0f, 1.0f) :
imm0.reg.data.f32;
break;
case TYPE_U16: res.data.f32 = (float) imm0.reg.data.u16; break;
case TYPE_U32: res.data.f32 = (float) imm0.reg.data.u32; break;
case TYPE_S16: res.data.f32 = (float) imm0.reg.data.s16; break;
case TYPE_S32: res.data.f32 = (float) imm0.reg.data.s32; break;
default:
return;
}
i->setSrc(0, bld.mkImm(res.data.f32));
break;
default:
return;
}
#undef CASE
i->setType(i->dType); /* Remove i->sType, which we don't need anymore */
i->op = OP_MOV;
i->saturate = 0;
i->src(0).mod = Modifier(0); /* Clear the already applied modifier */
break;
}
default:
return;
}
@ -1212,7 +1316,8 @@ private:
void handleRCP(Instruction *);
void handleSLCT(Instruction *);
void handleLOGOP(Instruction *);
void handleCVT(Instruction *);
void handleCVT_NEG(Instruction *);
void handleCVT_EXTBF(Instruction *);
void handleSUCLAMP(Instruction *);
BuildUtil bld;
@ -1463,12 +1568,12 @@ AlgebraicOpt::handleLOGOP(Instruction *logop)
// nv50:
// F2I(NEG(I2F(ABS(SET))))
void
AlgebraicOpt::handleCVT(Instruction *cvt)
AlgebraicOpt::handleCVT_NEG(Instruction *cvt)
{
Instruction *insn = cvt->getSrc(0)->getInsn();
if (cvt->sType != TYPE_F32 ||
cvt->dType != TYPE_S32 || cvt->src(0).mod != Modifier(0))
return;
Instruction *insn = cvt->getSrc(0)->getInsn();
if (!insn || insn->op != OP_NEG || insn->dType != TYPE_F32)
return;
if (insn->src(0).mod != Modifier(0))
@ -1498,6 +1603,104 @@ AlgebraicOpt::handleCVT(Instruction *cvt)
delete_Instruction(prog, cvt);
}
// Some shaders extract packed bytes out of words and convert them to
// e.g. float. The Fermi+ CVT instruction can extract those directly, as can
// nv50 for word sizes.
//
// CVT(EXTBF(x, byte/word))
// CVT(AND(bytemask, x))
// CVT(AND(bytemask, SHR(x, 8/16/24)))
// CVT(SHR(x, 16/24))
void
AlgebraicOpt::handleCVT_EXTBF(Instruction *cvt)
{
Instruction *insn = cvt->getSrc(0)->getInsn();
ImmediateValue imm;
Value *arg = NULL;
unsigned width, offset;
if ((cvt->sType != TYPE_U32 && cvt->sType != TYPE_S32) || !insn)
return;
if (insn->op == OP_EXTBF && insn->src(1).getImmediate(imm)) {
width = (imm.reg.data.u32 >> 8) & 0xff;
offset = imm.reg.data.u32 & 0xff;
arg = insn->getSrc(0);
if (width != 8 && width != 16)
return;
if (width == 8 && offset & 0x7)
return;
if (width == 16 && offset & 0xf)
return;
} else if (insn->op == OP_AND) {
int s;
if (insn->src(0).getImmediate(imm))
s = 0;
else if (insn->src(1).getImmediate(imm))
s = 1;
else
return;
if (imm.reg.data.u32 == 0xff)
width = 8;
else if (imm.reg.data.u32 == 0xffff)
width = 16;
else
return;
arg = insn->getSrc(!s);
Instruction *shift = arg->getInsn();
offset = 0;
if (shift && shift->op == OP_SHR &&
shift->sType == cvt->sType &&
shift->src(1).getImmediate(imm) &&
((width == 8 && (imm.reg.data.u32 & 0x7) == 0) ||
(width == 16 && (imm.reg.data.u32 & 0xf) == 0))) {
arg = shift->getSrc(0);
offset = imm.reg.data.u32;
}
} else if (insn->op == OP_SHR &&
insn->sType == cvt->sType &&
insn->src(1).getImmediate(imm)) {
arg = insn->getSrc(0);
if (imm.reg.data.u32 == 24) {
width = 8;
offset = 24;
} else if (imm.reg.data.u32 == 16) {
width = 16;
offset = 16;
} else {
return;
}
}
if (!arg)
return;
// Irrespective of what came earlier, we can undo a shift on the argument
// by adjusting the offset.
Instruction *shift = arg->getInsn();
if (shift && shift->op == OP_SHL &&
shift->src(1).getImmediate(imm) &&
((width == 8 && (imm.reg.data.u32 & 0x7) == 0) ||
(width == 16 && (imm.reg.data.u32 & 0xf) == 0)) &&
imm.reg.data.u32 <= offset) {
arg = shift->getSrc(0);
offset -= imm.reg.data.u32;
}
// The unpackSnorm lowering still leaves a few shifts behind, but it's too
// annoying to detect them.
if (width == 8) {
cvt->sType = cvt->sType == TYPE_U32 ? TYPE_U8 : TYPE_S8;
} else {
assert(width == 16);
cvt->sType = cvt->sType == TYPE_U32 ? TYPE_U16 : TYPE_S16;
}
cvt->setSrc(0, arg);
cvt->subOp = offset >> 3;
}
// SUCLAMP dst, (ADD b imm), k, 0 -> SUCLAMP dst, b, k, imm (if imm fits s6)
void
AlgebraicOpt::handleSUCLAMP(Instruction *insn)
@ -1568,7 +1771,9 @@ AlgebraicOpt::visit(BasicBlock *bb)
handleLOGOP(i);
break;
case OP_CVT:
handleCVT(i);
handleCVT_NEG(i);
if (prog->getTarget()->isOpSupported(OP_EXTBF, TYPE_U32))
handleCVT_EXTBF(i);
break;
case OP_SUCLAMP:
handleSUCLAMP(i);

5
src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
View file

@ -25,7 +25,6 @@
#include <stack>
#include <limits>
#include <tr1/unordered_set>
namespace nv50_ir {
@ -1551,7 +1550,7 @@ SpillCodeInserter::run(const std::list<ValuePair>& lst)
// Keep track of which instructions to delete later. Deleting them
// inside the loop is unsafe since a single instruction may have
// multiple destinations that all need to be spilled (like OP_SPLIT).
std::tr1::unordered_set<Instruction *> to_del;
unordered_set<Instruction *> to_del;
for (Value::DefIterator d = lval->defs.begin(); d != lval->defs.end();
++d) {
@ -1593,7 +1592,7 @@ SpillCodeInserter::run(const std::list<ValuePair>& lst)
}
}
for (std::tr1::unordered_set<Instruction *>::const_iterator it = to_del.begin();
for (unordered_set<Instruction *>::const_iterator it = to_del.begin();
it != to_del.end(); ++it)
delete_Instruction(func->getProgram(), *it);
}

48
src/gallium/drivers/nouveau/codegen/unordered_set.h Normal file
View file

@ -0,0 +1,48 @@
#ifndef __NV50_UNORDERED_SET_H__
#define __NV50_UNORDERED_SET_H__
#if (__cplusplus >= 201103L) || defined(ANDROID)
#include <unordered_set>
#else
#include <tr1/unordered_set>
#endif
namespace nv50_ir {
#if __cplusplus >= 201103L
using std::unordered_set;
#elif !defined(ANDROID)
using std::tr1::unordered_set;
#else // Android release before lollipop
using std::isfinite;
typedef std::tr1::unordered_set<void *> voidptr_unordered_set;
template <typename V>
class unordered_set : public voidptr_unordered_set {
public:
typedef voidptr_unordered_set _base;
typedef _base::iterator _biterator;
typedef _base::const_iterator const_biterator;
class iterator : public _biterator {
public:
iterator(const _biterator & i) : _biterator(i) {}
V operator*() const { return reinterpret_cast<V>(*_biterator(*this)); }
};
class const_iterator : public const_biterator {
public:
const_iterator(const iterator & i) : const_biterator(i) {}
const_iterator(const const_biterator & i) : const_biterator(i) {}
const V operator*() const { return reinterpret_cast<const V>(*const_biterator(*this)); }
};
iterator begin() { return _base::begin(); }
iterator end() { return _base::end(); }
const_iterator begin() const { return _base::begin(); }
const_iterator end() const { return _base::end(); }
};
#endif
} // namespace nv50_ir
#endif // __NV50_UNORDERED_SET_H__

4
src/gallium/drivers/nouveau/nouveau_compiler.c
View file

@ -190,6 +190,10 @@ main(int argc, char *argv[])
type = PIPE_SHADER_GEOMETRY;
else if (!strncmp(text, "COMP", 4))
type = PIPE_SHADER_COMPUTE;
else if (!strncmp(text, "TESS_CTRL", 9))
type = PIPE_SHADER_TESS_CTRL;
else if (!strncmp(text, "TESS_EVAL", 9))
type = PIPE_SHADER_TESS_EVAL;
else {
_debug_printf("Unrecognized TGSI header\n");
return 1;

10
src/gallium/drivers/nouveau/nv50/nv50_state.c
View file

@ -117,7 +117,6 @@ nv50_blend_state_create(struct pipe_context *pipe,
struct nv50_blend_stateobj *so = CALLOC_STRUCT(nv50_blend_stateobj);
int i;
bool emit_common_func = cso->rt[0].blend_enable;
uint32_t ms;
if (nv50_context(pipe)->screen->tesla->oclass >= NVA3_3D_CLASS) {
SB_BEGIN_3D(so, BLEND_INDEPENDENT, 1);
@ -189,15 +188,6 @@ nv50_blend_state_create(struct pipe_context *pipe,
SB_DATA (so, nv50_colormask(cso->rt[0].colormask));
}
ms = 0;
if (cso->alpha_to_coverage)
ms |= NV50_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
if (cso->alpha_to_one)
ms |= NV50_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
SB_BEGIN_3D(so, MULTISAMPLE_CTRL, 1);
SB_DATA (so, ms);
assert(so->size <= (sizeof(so->state) / sizeof(so->state[0])));
return so;
}

22
src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
View file

@ -1,4 +1,6 @@
#include "util/u_format.h"
#include "nv50/nv50_context.h"
#include "nv50/nv50_defs.xml.h"
@ -313,6 +315,25 @@ nv50_validate_derived_2(struct nv50_context *nv50)
}
}
static void
nv50_validate_derived_3(struct nv50_context *nv50)
{
struct nouveau_pushbuf *push = nv50->base.pushbuf;
struct pipe_framebuffer_state *fb = &nv50->framebuffer;
uint32_t ms = 0;
if ((!fb->nr_cbufs || !fb->cbufs[0] ||
!util_format_is_pure_integer(fb->cbufs[0]->format)) && nv50->blend) {
if (nv50->blend->pipe.alpha_to_coverage)
ms |= NV50_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
if (nv50->blend->pipe.alpha_to_one)
ms |= NV50_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
}
BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
PUSH_DATA (push, ms);
}
static void
nv50_validate_clip(struct nv50_context *nv50)
{
@ -474,6 +495,7 @@ static struct state_validate {
{ nv50_validate_derived_rs, NV50_NEW_FRAGPROG | NV50_NEW_RASTERIZER |
NV50_NEW_VERTPROG | NV50_NEW_GMTYPROG },
{ nv50_validate_derived_2, NV50_NEW_ZSA | NV50_NEW_FRAMEBUFFER },
{ nv50_validate_derived_3, NV50_NEW_BLEND | NV50_NEW_FRAMEBUFFER },
{ nv50_validate_clip, NV50_NEW_CLIP | NV50_NEW_RASTERIZER |
NV50_NEW_VERTPROG | NV50_NEW_GMTYPROG },
{ nv50_constbufs_validate, NV50_NEW_CONSTBUF },

2
src/gallium/drivers/nouveau/nv50/nv50_stateobj.h
View file

@ -19,7 +19,7 @@
struct nv50_blend_stateobj {
struct pipe_blend_state pipe;
int size;
uint32_t state[84]; // TODO: allocate less if !independent_blend_enable
uint32_t state[82]; // TODO: allocate less if !independent_blend_enable
};
struct nv50_rasterizer_stateobj {

20
src/gallium/drivers/nouveau/nv50/nv50_surface.c
View file

@ -68,6 +68,10 @@ nv50_2d_format(enum pipe_format format, bool dst, bool dst_src_equal)
return NV50_SURFACE_FORMAT_R16_UNORM;
case 4:
return NV50_SURFACE_FORMAT_BGRA8_UNORM;
case 8:
return NV50_SURFACE_FORMAT_RGBA16_FLOAT;
case 16:
return NV50_SURFACE_FORMAT_RGBA32_FLOAT;
default:
return 0;
}
@ -1003,6 +1007,8 @@ nv50_blitctx_prepare_state(struct nv50_blitctx *blit)
/* zsa state */
BEGIN_NV04(push, NV50_3D(DEPTH_TEST_ENABLE), 1);
PUSH_DATA (push, 0);
BEGIN_NV04(push, NV50_3D(DEPTH_BOUNDS_EN), 1);
PUSH_DATA (push, 0);
BEGIN_NV04(push, NV50_3D(STENCIL_ENABLE), 1);
PUSH_DATA (push, 0);
BEGIN_NV04(push, NV50_3D(ALPHA_TEST_ENABLE), 1);
@ -1387,18 +1393,24 @@ nv50_blit_eng2d(struct nv50_context *nv50, const struct pipe_blit_info *info)
PUSH_DATA (push, info->dst.box.z + i);
} else {
const unsigned z = info->dst.box.z + i;
const uint64_t address = dst->base.address +
dst->level[info->dst.level].offset +
z * dst->layer_stride;
BEGIN_NV04(push, NV50_2D(DST_ADDRESS_HIGH), 2);
PUSH_DATAh(push, dst->base.address + z * dst->layer_stride);
PUSH_DATA (push, dst->base.address + z * dst->layer_stride);
PUSH_DATAh(push, address);
PUSH_DATA (push, address);
}
if (src->layout_3d) {
/* not possible because of depth tiling */
assert(0);
} else {
const unsigned z = info->src.box.z + i;
const uint64_t address = src->base.address +
src->level[info->src.level].offset +
z * src->layer_stride;
BEGIN_NV04(push, NV50_2D(SRC_ADDRESS_HIGH), 2);
PUSH_DATAh(push, src->base.address + z * src->layer_stride);
PUSH_DATA (push, src->base.address + z * src->layer_stride);
PUSH_DATAh(push, address);
PUSH_DATA (push, address);
}
BEGIN_NV04(push, NV50_2D(BLIT_SRC_Y_INT), 1); /* trigger */
PUSH_DATA (push, srcy >> 32);

25
src/gallium/drivers/nouveau/nvc0/nvc0_context.c
View file

@ -132,6 +132,9 @@ nvc0_context_unreference_resources(struct nvc0_context *nvc0)
pipe_resource_reference(res, NULL);
}
util_dynarray_fini(&nvc0->global_residents);
if (nvc0->tcp_empty)
nvc0->base.pipe.delete_tcs_state(&nvc0->base.pipe, nvc0->tcp_empty);
}
static void
@ -306,13 +309,6 @@ nvc0_create(struct pipe_screen *pscreen, void *priv)
pipe->memory_barrier = nvc0_memory_barrier;
pipe->get_sample_position = nvc0_context_get_sample_position;
if (!screen->cur_ctx) {
nvc0->state = screen->save_state;
screen->cur_ctx = nvc0;
nouveau_pushbuf_bufctx(screen->base.pushbuf, nvc0->bufctx);
}
screen->base.pushbuf->kick_notify = nvc0_default_kick_notify;
nvc0_init_query_functions(nvc0);
nvc0_init_surface_functions(nvc0);
nvc0_init_state_functions(nvc0);
@ -326,6 +322,21 @@ nvc0_create(struct pipe_screen *pscreen, void *priv)
/* shader builtin library is per-screen, but we need a context for m2mf */
nvc0_program_library_upload(nvc0);
nvc0_program_init_tcp_empty(nvc0);
if (!nvc0->tcp_empty)
goto out_err;
/* set the empty tctl prog on next draw in case one is never set */
nvc0->dirty |= NVC0_NEW_TCTLPROG;
/* now that there are no more opportunities for errors, set the current
* context if there isn't already one.
*/
if (!screen->cur_ctx) {
nvc0->state = screen->save_state;
screen->cur_ctx = nvc0;
nouveau_pushbuf_bufctx(screen->base.pushbuf, nvc0->bufctx);
}
screen->base.pushbuf->kick_notify = nvc0_default_kick_notify;
/* add permanently resident buffers to bufctxts */

3
src/gallium/drivers/nouveau/nvc0/nvc0_context.h
View file

@ -128,6 +128,8 @@ struct nvc0_context {
struct nvc0_program *fragprog;
struct nvc0_program *compprog;
struct nvc0_program *tcp_empty;
struct nvc0_constbuf constbuf[6][NVC0_MAX_PIPE_CONSTBUFS];
uint16_t constbuf_dirty[6];
uint16_t constbuf_valid[6];
@ -227,6 +229,7 @@ void nvc0_program_destroy(struct nvc0_context *, struct nvc0_program *);
void nvc0_program_library_upload(struct nvc0_context *);
uint32_t nvc0_program_symbol_offset(const struct nvc0_program *,
uint32_t label);
void nvc0_program_init_tcp_empty(struct nvc0_context *);
/* nvc0_query.c */
void nvc0_init_query_functions(struct nvc0_context *);

17
src/gallium/drivers/nouveau/nvc0/nvc0_program.c
View file

@ -22,6 +22,8 @@
#include "pipe/p_defines.h"
#include "tgsi/tgsi_ureg.h"
#include "nvc0/nvc0_context.h"
#include "codegen/nv50_ir_driver.h"
@ -799,3 +801,18 @@ nvc0_program_symbol_offset(const struct nvc0_program *prog, uint32_t label)
return prog->code_base + base + syms[i].offset;
return prog->code_base; /* no symbols or symbol not found */
}
void
nvc0_program_init_tcp_empty(struct nvc0_context *nvc0)
{
struct ureg_program *ureg;
ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
if (!ureg)
return;
ureg_property(ureg, TGSI_PROPERTY_TCS_VERTICES_OUT, 1);
ureg_END(ureg);
nvc0->tcp_empty = ureg_create_shader_and_destroy(ureg, &nvc0->base.pipe);
}

7
src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
View file

@ -148,8 +148,13 @@ nvc0_tctlprog_validate(struct nvc0_context *nvc0)
BEGIN_NVC0(push, NVC0_3D(SP_GPR_ALLOC(2)), 1);
PUSH_DATA (push, tp->num_gprs);
} else {
BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
tp = nvc0->tcp_empty;
/* not a whole lot we can do to handle this failure */
if (!nvc0_program_validate(nvc0, tp))
assert(!"unable to validate empty tcp");
BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 2);
PUSH_DATA (push, 0x20);
PUSH_DATA (push, tp->code_base);
}
nvc0_program_update_context_state(nvc0, tp, 1);
}

12
src/gallium/drivers/nouveau/nvc0/nvc0_state.c
View file

@ -90,7 +90,6 @@ nvc0_blend_state_create(struct pipe_context *pipe,
struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
int i;
int r; /* reference */
uint32_t ms;
uint8_t blend_en = 0;
bool indep_masks = false;
bool indep_funcs = false;
@ -176,15 +175,6 @@ nvc0_blend_state_create(struct pipe_context *pipe,
}
}
ms = 0;
if (cso->alpha_to_coverage)
ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
if (cso->alpha_to_one)
ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
SB_BEGIN_3D(so, MULTISAMPLE_CTRL, 1);
SB_DATA (so, ms);
assert(so->size <= (sizeof(so->state) / sizeof(so->state[0])));
return so;
}
@ -234,7 +224,7 @@ nvc0_rasterizer_state_create(struct pipe_context *pipe,
SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
if (cso->line_smooth)
if (cso->line_smooth || cso->multisample)
SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
else
SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);

21
src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c
View file

@ -1,4 +1,5 @@
#include "util/u_format.h"
#include "util/u_math.h"
#include "nvc0/nvc0_context.h"
@ -554,6 +555,25 @@ nvc0_validate_derived_2(struct nvc0_context *nvc0)
}
}
static void
nvc0_validate_derived_3(struct nvc0_context *nvc0)
{
struct nouveau_pushbuf *push = nvc0->base.pushbuf;
struct pipe_framebuffer_state *fb = &nvc0->framebuffer;
uint32_t ms = 0;
if ((!fb->nr_cbufs || !fb->cbufs[0] ||
!util_format_is_pure_integer(fb->cbufs[0]->format)) && nvc0->blend) {
if (nvc0->blend->pipe.alpha_to_coverage)
ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
if (nvc0->blend->pipe.alpha_to_one)
ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
}
BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
PUSH_DATA (push, ms);
}
static void
nvc0_validate_tess_state(struct nvc0_context *nvc0)
{
@ -628,6 +648,7 @@ static struct state_validate {
{ nvc0_validate_derived_1, NVC0_NEW_FRAGPROG | NVC0_NEW_ZSA |
NVC0_NEW_RASTERIZER },
{ nvc0_validate_derived_2, NVC0_NEW_ZSA | NVC0_NEW_FRAMEBUFFER },
{ nvc0_validate_derived_3, NVC0_NEW_BLEND | NVC0_NEW_FRAMEBUFFER },
{ nvc0_validate_clip, NVC0_NEW_CLIP | NVC0_NEW_RASTERIZER |
NVC0_NEW_VERTPROG |
NVC0_NEW_TEVLPROG |

2
src/gallium/drivers/nouveau/nvc0/nvc0_stateobj.h
View file

@ -17,7 +17,7 @@
struct nvc0_blend_stateobj {
struct pipe_blend_state pipe;
int size;
uint32_t state[72];
uint32_t state[70];
};
struct nvc0_rasterizer_stateobj {

15
src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
View file

@ -887,6 +887,7 @@ nvc0_blitctx_prepare_state(struct nvc0_blitctx *blit)
/* zsa state */
IMMED_NVC0(push, NVC0_3D(DEPTH_TEST_ENABLE), 0);
IMMED_NVC0(push, NVC0_3D(DEPTH_BOUNDS_EN), 0);
IMMED_NVC0(push, NVC0_3D(STENCIL_ENABLE), 0);
IMMED_NVC0(push, NVC0_3D(ALPHA_TEST_ENABLE), 0);
@ -1336,18 +1337,24 @@ nvc0_blit_eng2d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
PUSH_DATA (push, info->dst.box.z + i);
} else {
const unsigned z = info->dst.box.z + i;
const uint64_t address = dst->base.address +
dst->level[info->dst.level].offset +
z * dst->layer_stride;
BEGIN_NVC0(push, NVC0_2D(DST_ADDRESS_HIGH), 2);
PUSH_DATAh(push, dst->base.address + z * dst->layer_stride);
PUSH_DATA (push, dst->base.address + z * dst->layer_stride);
PUSH_DATAh(push, address);
PUSH_DATA (push, address);
}
if (src->layout_3d) {
/* not possible because of depth tiling */
assert(0);
} else {
const unsigned z = info->src.box.z + i;
const uint64_t address = src->base.address +
src->level[info->src.level].offset +
z * src->layer_stride;
BEGIN_NVC0(push, NVC0_2D(SRC_ADDRESS_HIGH), 2);
PUSH_DATAh(push, src->base.address + z * src->layer_stride);
PUSH_DATA (push, src->base.address + z * src->layer_stride);
PUSH_DATAh(push, address);
PUSH_DATA (push, address);
}
BEGIN_NVC0(push, NVC0_2D(BLIT_SRC_Y_INT), 1); /* trigger */
PUSH_DATA (push, srcy >> 32);

3
src/gallium/drivers/r300/compiler/radeon_pair_regalloc.c
View file

@ -693,7 +693,8 @@ void rc_init_regalloc_state(struct rc_regalloc_state *s)
};
/* Allocate the main ra data structure */
s->regs = ra_alloc_reg_set(NULL, R500_PFS_NUM_TEMP_REGS * RC_MASK_XYZW);
s->regs = ra_alloc_reg_set(NULL, R500_PFS_NUM_TEMP_REGS * RC_MASK_XYZW,
true);
/* Create the register classes */
for (i = 0; i < RC_REG_CLASS_COUNT; i++) {

3
src/gallium/drivers/r300/r300_blit.c
View file

@ -667,7 +667,8 @@ static void r300_resource_copy_region(struct pipe_context *pipe,
r300_blitter_begin(r300, R300_COPY);
util_blitter_blit_generic(r300->blitter, dst_view, &dstbox,
src_view, src_box, src_width0, src_height0,
PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL);
PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
FALSE);
r300_blitter_end(r300);
pipe_surface_reference(&dst_view, NULL);

3
src/gallium/drivers/r600/r600_blit.c
View file

@ -732,7 +732,8 @@ void r600_resource_copy_region(struct pipe_context *ctx,
r600_blitter_begin(ctx, R600_COPY_TEXTURE);
util_blitter_blit_generic(rctx->blitter, dst_view, &dstbox,
src_view, src_box, src_width0, src_height0,
PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL);
PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
FALSE);
r600_blitter_end(ctx);
pipe_surface_reference(&dst_view, NULL);

2
src/gallium/drivers/r600/r600_isa.h
View file

@ -262,7 +262,7 @@ static const struct alu_op_info alu_op_table[] = {
{"PRED_SETNE_PUSH_INT", 2, { 0x4D, 0x4D },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_NE | AF_INT_CMP },
{"PRED_SETLT_PUSH_INT", 2, { 0x4E, 0x4E },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_LT | AF_INT_CMP },
{"PRED_SETLE_PUSH_INT", 2, { 0x4F, 0x4F },{ AF_VS, AF_VS, AF_VS, AF_VS}, AF_PRED_PUSH | AF_CC_LE | AF_INT_CMP },
{"FLT_TO_INT", 1, { 0x6B, 0x50 },{ AF_S, AF_S, AF_VS, AF_VS}, AF_INT_DST | AF_CVT },
{"FLT_TO_INT", 1, { 0x6B, 0x50 },{ AF_S, AF_S, AF_V, AF_V}, AF_INT_DST | AF_CVT },
{"BFREV_INT", 1, { -1, 0x51 },{ 0, 0, AF_VS, AF_VS}, AF_INT_DST },
{"ADDC_UINT", 2, { -1, 0x52 },{ 0, 0, AF_VS, AF_VS}, AF_UINT_DST },
{"SUBB_UINT", 2, { -1, 0x53 },{ 0, 0, AF_VS, AF_VS}, AF_UINT_DST },

4
src/gallium/drivers/r600/r600_pipe.h
View file

@ -90,7 +90,7 @@
struct r600_context;
struct r600_bytecode;
struct r600_shader_key;
union r600_shader_key;
/* This is an atom containing GPU commands that never change.
* This is supposed to be copied directly into the CS. */
@ -643,7 +643,7 @@ void r600_resource_copy_region(struct pipe_context *ctx,
/* r600_shader.c */
int r600_pipe_shader_create(struct pipe_context *ctx,
struct r600_pipe_shader *shader,
struct r600_shader_key key);
union r600_shader_key key);
void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);

34
src/gallium/drivers/r600/r600_shader.c
View file

@ -62,7 +62,7 @@ The compiler must issue the source argument to slots z, y, and x
static int r600_shader_from_tgsi(struct r600_context *rctx,
struct r600_pipe_shader *pipeshader,
struct r600_shader_key key);
union r600_shader_key key);
static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
@ -133,7 +133,7 @@ static int store_shader(struct pipe_context *ctx,
int r600_pipe_shader_create(struct pipe_context *ctx,
struct r600_pipe_shader *shader,
struct r600_shader_key key)
union r600_shader_key key)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_shader_selector *sel = shader->selector;
@ -141,7 +141,7 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
bool dump = r600_can_dump_shader(&rctx->screen->b, sel->tokens);
unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
unsigned export_shader = key.vs_as_es;
unsigned export_shader = key.vs.as_es;
shader->shader.bc.isa = rctx->isa;
@ -1802,7 +1802,7 @@ static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, bool ind)
static int r600_shader_from_tgsi(struct r600_context *rctx,
struct r600_pipe_shader *pipeshader,
struct r600_shader_key key)
union r600_shader_key key)
{
struct r600_screen *rscreen = rctx->screen;
struct r600_shader *shader = &pipeshader->shader;
@ -1816,7 +1816,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
unsigned opcode;
int i, j, k, r = 0;
int next_param_base = 0, next_clip_base;
int max_color_exports = MAX2(key.nr_cbufs, 1);
int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
/* Declarations used by llvm code */
bool use_llvm = false;
bool indirect_gprs;
@ -1830,8 +1830,8 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
ctx.shader = shader;
ctx.native_integers = true;
shader->vs_as_gs_a = key.vs_as_gs_a;
shader->vs_as_es = key.vs_as_es;
shader->vs_as_gs_a = key.vs.as_gs_a;
shader->vs_as_es = key.vs.as_es;
r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
rscreen->has_compressed_msaa_texturing);
@ -1844,9 +1844,9 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
shader->processor_type = ctx.type;
ctx.bc->type = shader->processor_type;
ring_outputs = key.vs_as_es || (ctx.type == TGSI_PROCESSOR_GEOMETRY);
ring_outputs = key.vs.as_es || (ctx.type == TGSI_PROCESSOR_GEOMETRY);
if (key.vs_as_es) {
if (key.vs.as_es) {
ctx.gs_for_vs = &rctx->gs_shader->current->shader;
} else {
ctx.gs_for_vs = NULL;
@ -1866,7 +1866,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
shader->nr_ps_color_exports = 0;
shader->nr_ps_max_color_exports = 0;
shader->two_side = key.color_two_side;
shader->two_side = key.ps.color_two_side;
/* register allocations */
/* Values [0,127] correspond to GPR[0..127].
@ -1970,7 +1970,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
shader->fs_write_all = FALSE;
if (shader->vs_as_gs_a)
vs_add_primid_output(&ctx, key.vs_prim_id_out);
vs_add_primid_output(&ctx, key.vs.prim_id_out);
while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
tgsi_parse_token(&ctx.parse);
@ -2091,7 +2091,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN);
radeon_llvm_ctx.stream_outputs = &so;
radeon_llvm_ctx.alpha_to_one = key.alpha_to_one;
radeon_llvm_ctx.alpha_to_one = key.ps.alpha_to_one;
radeon_llvm_ctx.has_compressed_msaa_texturing =
ctx.bc->has_compressed_msaa_texturing;
mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
@ -2270,7 +2270,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
convert_edgeflag_to_int(&ctx);
if (ring_outputs) {
if (key.vs_as_es)
if (key.vs.as_es)
emit_gs_ring_writes(&ctx, FALSE);
} else {
/* Export output */
@ -2386,7 +2386,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
j--;
continue;
}
output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
output[j].array_base = shader->output[i].sid;
output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
shader->nr_ps_color_exports++;
@ -2399,7 +2399,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
output[j].swizzle_x = 0;
output[j].swizzle_y = 1;
output[j].swizzle_z = 2;
output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
output[j].burst_count = 1;
output[j].array_base = k;
output[j].op = CF_OP_EXPORT;
@ -6151,10 +6151,10 @@ static int tgsi_cmp(struct r600_shader_ctx *ctx)
r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
if (r)
return r;
r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[2]);
r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
if (r)
return r;
r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[2], &ctx->src[1]);
r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
if (r)
return r;
tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);

20
src/gallium/drivers/r600/r600_shader.h
View file

@ -95,13 +95,17 @@ struct r600_shader {
struct r600_shader_array * arrays;
};
struct r600_shader_key {
unsigned color_two_side:1;
unsigned alpha_to_one:1;
unsigned nr_cbufs:4;
unsigned vs_as_es:1;
unsigned vs_as_gs_a:1;
unsigned vs_prim_id_out:8;
union r600_shader_key {
struct {
unsigned nr_cbufs:4;
unsigned color_two_side:1;
unsigned alpha_to_one:1;
} ps;
struct {
unsigned prim_id_out:8;
unsigned as_es:1; /* export shader */
unsigned as_gs_a:1;
} vs;
};
struct r600_shader_array {
@ -122,7 +126,7 @@ struct r600_pipe_shader {
unsigned flatshade;
unsigned pa_cl_vs_out_cntl;
unsigned nr_ps_color_outputs;
struct r600_shader_key key;
union r600_shader_key key;
unsigned db_shader_control;
unsigned ps_depth_export;
unsigned enabled_stream_buffers_mask;

42
src/gallium/drivers/r600/r600_state_common.c
View file

@ -702,29 +702,39 @@ void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
}
/* Compute the key for the hw shader variant */
static inline struct r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
static inline union r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
struct r600_pipe_shader_selector * sel)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_shader_key key;
union r600_shader_key key;
memset(&key, 0, sizeof(key));
if (sel->type == PIPE_SHADER_FRAGMENT) {
key.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
key.alpha_to_one = rctx->alpha_to_one &&
rctx->rasterizer && rctx->rasterizer->multisample_enable &&
!rctx->framebuffer.cb0_is_integer;
key.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
/* Dual-source blending only makes sense with nr_cbufs == 1. */
if (key.nr_cbufs == 1 && rctx->dual_src_blend)
key.nr_cbufs = 2;
} else if (sel->type == PIPE_SHADER_VERTEX) {
key.vs_as_es = (rctx->gs_shader != NULL);
switch (sel->type) {
case PIPE_SHADER_VERTEX: {
key.vs.as_es = (rctx->gs_shader != NULL);
if (rctx->ps_shader->current->shader.gs_prim_id_input && !rctx->gs_shader) {
key.vs_as_gs_a = true;
key.vs_prim_id_out = rctx->ps_shader->current->shader.input[rctx->ps_shader->current->shader.ps_prim_id_input].spi_sid;
key.vs.as_gs_a = true;
key.vs.prim_id_out = rctx->ps_shader->current->shader.input[rctx->ps_shader->current->shader.ps_prim_id_input].spi_sid;
}
break;
}
case PIPE_SHADER_GEOMETRY:
break;
case PIPE_SHADER_FRAGMENT: {
key.ps.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
key.ps.alpha_to_one = rctx->alpha_to_one &&
rctx->rasterizer && rctx->rasterizer->multisample_enable &&
!rctx->framebuffer.cb0_is_integer;
key.ps.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
/* Dual-source blending only makes sense with nr_cbufs == 1. */
if (key.ps.nr_cbufs == 1 && rctx->dual_src_blend)
key.ps.nr_cbufs = 2;
break;
}
default:
assert(0);
}
return key;
}
@ -734,7 +744,7 @@ static int r600_shader_select(struct pipe_context *ctx,
struct r600_pipe_shader_selector* sel,
bool *dirty)
{
struct r600_shader_key key;
union r600_shader_key key;
struct r600_pipe_shader * shader = NULL;
int r;

5
src/gallium/drivers/radeon/radeon_uvd.c
View file

@ -209,8 +209,6 @@ static uint32_t profile2stream_type(struct ruvd_decoder *dec, unsigned family)
static unsigned calc_ctx_size(struct ruvd_decoder *dec)
{
unsigned width_in_mb, height_in_mb, ctx_size;
unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
@ -223,8 +221,7 @@ static unsigned calc_ctx_size(struct ruvd_decoder *dec)
width = align (width, 16);
height = align (height, 16);
ctx_size = ((width + 255) / 16)*((height + 255) / 16) * 16 * max_references + 52 * 1024;
return ctx_size;
return ((width + 255) / 16) * ((height + 255) / 16) * 16 * max_references + 52 * 1024;
}
/* calculate size of reference picture buffer */

3
src/gallium/drivers/radeonsi/si_blit.c
View file

@ -586,7 +586,8 @@ void si_resource_copy_region(struct pipe_context *ctx,
si_blitter_begin(ctx, SI_COPY);
util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
src_view, src_box, src_width0, src_height0,
PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL);
PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
FALSE);
si_blitter_end(ctx);
pipe_surface_reference(&dst_view, NULL);

19
src/gallium/drivers/radeonsi/si_shader.c
View file

@ -2277,7 +2277,7 @@ static void tex_fetch_args(
unsigned sampler_index;
unsigned num_deriv_channels = 0;
bool has_offset = HAVE_LLVM >= 0x0305 ? inst->Texture.NumOffsets > 0 : false;
LLVMValueRef res_ptr, samp_ptr;
LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
@ -2293,9 +2293,19 @@ static void tex_fetch_args(
samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
samp_ptr = build_indexed_load_const(si_shader_ctx, samp_ptr, ind_index);
if (target == TGSI_TEXTURE_2D_MSAA ||
target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
ind_index = LLVMBuildAdd(gallivm->builder, ind_index,
lp_build_const_int32(gallivm,
SI_FMASK_TEX_OFFSET), "");
fmask_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
fmask_ptr = build_indexed_load_const(si_shader_ctx, res_ptr, ind_index);
}
} else {
res_ptr = si_shader_ctx->resources[sampler_index];
samp_ptr = si_shader_ctx->samplers[sampler_index];
fmask_ptr = si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index];
}
if (target == TGSI_TEXTURE_BUFFER) {
@ -2493,7 +2503,7 @@ static void tex_fetch_args(
txf_emit_data.dst_type = LLVMVectorType(
LLVMInt32TypeInContext(gallivm->context), 4);
txf_emit_data.args[0] = lp_build_gather_values(gallivm, txf_address, txf_count);
txf_emit_data.args[1] = si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index];
txf_emit_data.args[1] = fmask_ptr;
txf_emit_data.args[2] = lp_build_const_int32(gallivm, inst.Texture.Texture);
txf_emit_data.arg_count = 3;
@ -2524,8 +2534,7 @@ static void tex_fetch_args(
* resource descriptor is 0 (invalid),
*/
LLVMValueRef fmask_desc =
LLVMBuildBitCast(gallivm->builder,
si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index],
LLVMBuildBitCast(gallivm->builder, fmask_ptr,
LLVMVectorType(uint_bld->elem_type, 8), "");
LLVMValueRef fmask_word1 =
@ -3973,7 +3982,7 @@ static void si_dump_key(unsigned shader, union si_shader_key *key)
fprintf(stderr, " es_enabled_outputs = 0x%"PRIx64"\n",
key->vs.es_enabled_outputs);
fprintf(stderr, " as_es = %u\n", key->vs.as_es);
fprintf(stderr, " as_es = %u\n", key->vs.as_ls);
fprintf(stderr, " as_ls = %u\n", key->vs.as_ls);
break;
case PIPE_SHADER_TESS_CTRL:

1
src/gallium/drivers/vc4/vc4_context.h
View file

@ -270,6 +270,7 @@ struct vc4_context {
struct ra_regs *regs;
unsigned int reg_class_any;
unsigned int reg_class_a_or_b_or_acc;
unsigned int reg_class_r4_or_a;
unsigned int reg_class_a;

33
src/gallium/drivers/vc4/vc4_opt_algebraic.c
View file

@ -143,15 +143,6 @@ qir_opt_algebraic(struct vc4_compile *c)
case QOP_SEL_X_Y_ZC:
case QOP_SEL_X_Y_NS:
case QOP_SEL_X_Y_NC:
if (qir_reg_equals(inst->src[0], inst->src[1])) {
/* Turn "dst = (sf == x) ? a : a)" into
* "dst = a"
*/
replace_with_mov(c, inst, inst->src[1]);
progress = true;
break;
}
if (is_zero(c, inst->src[1])) {
/* Replace references to a 0 uniform value
* with the SEL_X_0 equivalent.
@ -207,6 +198,7 @@ qir_opt_algebraic(struct vc4_compile *c)
/* FADD(a, FSUB(0, b)) -> FSUB(a, b) */
if (inst->src[1].file == QFILE_TEMP &&
c->defs[inst->src[1].index] &&
c->defs[inst->src[1].index]->op == QOP_FSUB) {
struct qinst *fsub = c->defs[inst->src[1].index];
if (is_zero(c, fsub->src[0])) {
@ -221,6 +213,7 @@ qir_opt_algebraic(struct vc4_compile *c)
/* FADD(FSUB(0, b), a) -> FSUB(a, b) */
if (inst->src[0].file == QFILE_TEMP &&
c->defs[inst->src[0].index] &&
c->defs[inst->src[0].index]->op == QOP_FSUB) {
struct qinst *fsub = c->defs[inst->src[0].index];
if (is_zero(c, fsub->src[0])) {
@ -236,18 +229,20 @@ qir_opt_algebraic(struct vc4_compile *c)
break;
case QOP_FMUL:
if (replace_x_0_with_0(c, inst, 0) ||
replace_x_0_with_0(c, inst, 1) ||
fmul_replace_one(c, inst, 0) ||
fmul_replace_one(c, inst, 1)) {
if (!inst->dst.pack &&
(replace_x_0_with_0(c, inst, 0) ||
replace_x_0_with_0(c, inst, 1) ||
fmul_replace_one(c, inst, 0) ||
fmul_replace_one(c, inst, 1))) {
progress = true;
break;
}
break;
case QOP_MUL24:
if (replace_x_0_with_0(c, inst, 0) ||
replace_x_0_with_0(c, inst, 1)) {
if (!inst->dst.pack &&
(replace_x_0_with_0(c, inst, 0) ||
replace_x_0_with_0(c, inst, 1))) {
progress = true;
break;
}
@ -280,6 +275,14 @@ qir_opt_algebraic(struct vc4_compile *c)
}
break;
case QOP_RCP:
if (is_1f(c, inst->src[0])) {
replace_with_mov(c, inst, inst->src[0]);
progress = true;
break;
}
break;
default:
break;
}

22
src/gallium/drivers/vc4/vc4_opt_copy_propagation.c
View file

@ -39,21 +39,27 @@ qir_opt_copy_propagation(struct vc4_compile *c)
{
bool progress = false;
bool debug = false;
struct qreg *movs = calloc(c->num_temps, sizeof(struct qreg));
list_for_each_entry(struct qinst, inst, &c->instructions, link) {
for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
int index = inst->src[i].index;
if (inst->src[i].file == QFILE_TEMP &&
(movs[index].file == QFILE_TEMP ||
movs[index].file == QFILE_UNIF)) {
c->defs[index] &&
c->defs[index]->op == QOP_MOV &&
(c->defs[index]->src[0].file == QFILE_TEMP ||
c->defs[index]->src[0].file == QFILE_UNIF)) {
/* If it has a pack, it shouldn't be an SSA
* def.
*/
assert(!c->defs[index]->dst.pack);
if (debug) {
fprintf(stderr, "Copy propagate: ");
qir_dump_inst(c, inst);
fprintf(stderr, "\n");
}
inst->src[i] = movs[index];
inst->src[i] = c->defs[index]->src[0];
if (debug) {
fprintf(stderr, "to: ");
@ -64,14 +70,6 @@ qir_opt_copy_propagation(struct vc4_compile *c)
progress = true;
}
}
if (inst->op == QOP_MOV &&
inst->dst.file == QFILE_TEMP &&
inst->src[0].file != QFILE_VPM) {
movs[inst->dst.index] = inst->src[0];
}
}
free(movs);
return progress;
}

18
src/gallium/drivers/vc4/vc4_opt_vpm_writes.c
View file

@ -68,7 +68,7 @@ qir_opt_vpm_writes(struct vc4_compile *c)
continue;
struct qinst *inst = c->defs[temp];
if (qir_is_multi_instruction(inst))
if (!inst || qir_is_multi_instruction(inst))
continue;
if (qir_depends_on_flags(inst) || inst->sf)
@ -79,22 +79,6 @@ qir_opt_vpm_writes(struct vc4_compile *c)
continue;
}
/* A QOP_TEX_RESULT destination is r4, so we can't move
* accesses to it past another QOP_TEX_RESULT which would
* update it.
*/
int src;
for (src = 0; src < qir_get_op_nsrc(inst->op); src++) {
if (inst->src[src].file == QFILE_TEMP) {
if (c->defs[inst->src[src].index]->op ==
QOP_TEX_RESULT) {
break;
}
}
}
if (src != qir_get_op_nsrc(inst->op))
continue;
/* Move the generating instruction to the end of the program
* to maintain the order of the VPM writes.
*/

96
src/gallium/drivers/vc4/vc4_program.c
View file

@ -818,6 +818,72 @@ declare_uniform_range(struct vc4_compile *c, uint32_t start, uint32_t size)
c->ubo_ranges[array_id].used = false;
}
static bool
ntq_src_is_only_ssa_def_user(nir_src *src)
{
if (!src->is_ssa)
return false;
if (!list_empty(&src->ssa->if_uses))
return false;
return (src->ssa->uses.next == &src->use_link &&
src->ssa->uses.next->next == &src->ssa->uses);
}
/**
* In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
* bit set.
*
* However, as an optimization, it tries to find the instructions generating
* the sources to be packed and just emit the pack flag there, if possible.
*/
static void
ntq_emit_pack_unorm_4x8(struct vc4_compile *c, nir_alu_instr *instr)
{
struct qreg result = qir_get_temp(c);
struct nir_alu_instr *vec4 = NULL;
/* If packing from a vec4 op (as expected), identify it so that we can
* peek back at what generated its sources.
*/
if (instr->src[0].src.is_ssa &&
instr->src[0].src.ssa->parent_instr->type == nir_instr_type_alu &&
nir_instr_as_alu(instr->src[0].src.ssa->parent_instr)->op ==
nir_op_vec4) {
vec4 = nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
}
for (int i = 0; i < 4; i++) {
int swiz = instr->src[0].swizzle[i];
struct qreg src;
if (vec4) {
src = ntq_get_src(c, vec4->src[swiz].src,
vec4->src[swiz].swizzle[0]);
} else {
src = ntq_get_src(c, instr->src[0].src, swiz);
}
if (vec4 &&
ntq_src_is_only_ssa_def_user(&vec4->src[swiz].src) &&
src.file == QFILE_TEMP &&
c->defs[src.index] &&
qir_is_mul(c->defs[src.index]) &&
!c->defs[src.index]->dst.pack) {
struct qinst *rewrite = c->defs[src.index];
c->defs[src.index] = NULL;
rewrite->dst = result;
rewrite->dst.pack = QPU_PACK_MUL_8A + i;
continue;
}
qir_PACK_8_F(c, result, src, i);
}
struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
*dest = result;
}
static void
ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
{
@ -839,17 +905,7 @@ ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
}
if (instr->op == nir_op_pack_unorm_4x8) {
struct qreg result;
for (int i = 0; i < 4; i++) {
struct qreg src = ntq_get_src(c, instr->src[0].src,
instr->src[0].swizzle[i]);
if (i == 0)
result = qir_PACK_8888_F(c, src);
else
result = qir_PACK_8_F(c, result, src, i);
}
struct qreg *dest = ntq_get_dest(c, &instr->dest.dest);
*dest = result;
ntq_emit_pack_unorm_4x8(c, instr);
return;
}
@ -1130,20 +1186,24 @@ emit_frag_end(struct vc4_compile *c)
static void
emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
{
struct qreg xyi[2];
struct qreg packed = qir_get_temp(c);
for (int i = 0; i < 2; i++) {
struct qreg scale =
qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
xyi[i] = qir_FTOI(c, qir_FMUL(c,
qir_FMUL(c,
c->outputs[c->output_position_index + i],
scale),
rcp_w));
struct qreg packed_chan = packed;
packed_chan.pack = QPU_PACK_A_16A + i;
qir_FTOI_dest(c, packed_chan,
qir_FMUL(c,
qir_FMUL(c,
c->outputs[c->output_position_index + i],
scale),
rcp_w));
}
qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));
qir_VPM_WRITE(c, packed);
}
static void

38
src/gallium/drivers/vc4/vc4_qir.c
View file

@ -71,12 +71,11 @@ static const struct qir_op_info qir_op_info[] = {
[QOP_RSQ] = { "rsq", 1, 1, false, true },
[QOP_EXP2] = { "exp2", 1, 2, false, true },
[QOP_LOG2] = { "log2", 1, 2, false, true },
[QOP_PACK_8888_F] = { "pack_8888_f", 1, 1, false, true },
[QOP_PACK_8A_F] = { "pack_8a_f", 1, 2, false, true },
[QOP_PACK_8B_F] = { "pack_8b_f", 1, 2, false, true },
[QOP_PACK_8C_F] = { "pack_8c_f", 1, 2, false, true },
[QOP_PACK_8D_F] = { "pack_8d_f", 1, 2, false, true },
[QOP_PACK_SCALED] = { "pack_scaled", 1, 2, false, true },
[QOP_PACK_8888_F] = { "pack_8888_f", 1, 1 },
[QOP_PACK_8A_F] = { "pack_8a_f", 1, 1 },
[QOP_PACK_8B_F] = { "pack_8b_f", 1, 1 },
[QOP_PACK_8C_F] = { "pack_8c_f", 1, 1 },
[QOP_PACK_8D_F] = { "pack_8d_f", 1, 1 },
[QOP_TLB_DISCARD_SETUP] = { "discard", 0, 1, true },
[QOP_TLB_STENCIL_SETUP] = { "tlb_stencil_setup", 0, 1, true },
[QOP_TLB_Z_WRITE] = { "tlb_z", 0, 1, true },
@ -168,6 +167,18 @@ qir_is_multi_instruction(struct qinst *inst)
return qir_op_info[inst->op].multi_instruction;
}
bool
qir_is_mul(struct qinst *inst)
{
switch (inst->op) {
case QOP_FMUL:
case QOP_MUL24:
return true;
default:
return false;
}
}
bool
qir_is_tex(struct qinst *inst)
{
@ -273,6 +284,14 @@ qir_dump_inst(struct vc4_compile *c, struct qinst *inst)
inst->sf ? ".sf" : "");
qir_print_reg(c, inst->dst, true);
if (inst->dst.pack) {
if (inst->dst.pack) {
if (qir_is_mul(inst))
vc4_qpu_disasm_pack_mul(stderr, inst->dst.pack);
else
vc4_qpu_disasm_pack_a(stderr, inst->dst.pack);
}
}
for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
fprintf(stderr, ", ");
qir_print_reg(c, inst->src[i], false);
@ -348,7 +367,7 @@ qir_emit(struct vc4_compile *c, struct qinst *inst)
if (inst->dst.file == QFILE_TEMP)
c->defs[inst->dst.index] = inst;
list_addtail(&inst->link, &c->instructions);
qir_emit_nodef(c, inst);
}
bool
@ -389,8 +408,11 @@ qir_remove_instruction(struct vc4_compile *c, struct qinst *qinst)
struct qreg
qir_follow_movs(struct vc4_compile *c, struct qreg reg)
{
while (reg.file == QFILE_TEMP && c->defs[reg.index]->op == QOP_MOV)
while (reg.file == QFILE_TEMP &&
c->defs[reg.index] &&
c->defs[reg.index]->op == QOP_MOV) {
reg = c->defs[reg.index]->src[0];
}
return reg;
}

47
src/gallium/drivers/vc4/vc4_qir.h
View file

@ -58,6 +58,7 @@ enum qfile {
struct qreg {
enum qfile file;
uint32_t index;
int pack;
};
enum qop {
@ -104,7 +105,6 @@ enum qop {
QOP_LOG2,
QOP_VW_SETUP,
QOP_VR_SETUP,
QOP_PACK_SCALED,
QOP_PACK_8888_F,
QOP_PACK_8A_F,
QOP_PACK_8B_F,
@ -444,13 +444,20 @@ struct qreg qir_uniform(struct vc4_compile *c,
enum quniform_contents contents,
uint32_t data);
void qir_reorder_uniforms(struct vc4_compile *c);
void qir_emit(struct vc4_compile *c, struct qinst *inst);
static inline void qir_emit_nodef(struct vc4_compile *c, struct qinst *inst)
{
list_addtail(&inst->link, &c->instructions);
}
struct qreg qir_get_temp(struct vc4_compile *c);
int qir_get_op_nsrc(enum qop qop);
bool qir_reg_equals(struct qreg a, struct qreg b);
bool qir_has_side_effects(struct vc4_compile *c, struct qinst *inst);
bool qir_has_side_effect_reads(struct vc4_compile *c, struct qinst *inst);
bool qir_is_multi_instruction(struct qinst *inst);
bool qir_is_mul(struct qinst *inst);
bool qir_is_tex(struct qinst *inst);
bool qir_depends_on_flags(struct qinst *inst);
bool qir_writes_r4(struct qinst *inst);
@ -509,6 +516,12 @@ qir_##name(struct vc4_compile *c, struct qreg a) \
struct qreg t = qir_get_temp(c); \
qir_emit(c, qir_inst(QOP_##name, t, a, c->undef)); \
return t; \
} \
static inline void \
qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
struct qreg a) \
{ \
qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, c->undef)); \
}
#define QIR_ALU2(name) \
@ -518,6 +531,12 @@ qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
struct qreg t = qir_get_temp(c); \
qir_emit(c, qir_inst(QOP_##name, t, a, b)); \
return t; \
} \
static inline void \
qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
struct qreg a, struct qreg b) \
{ \
qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, b)); \
}
#define QIR_NODST_1(name) \
@ -534,6 +553,14 @@ qir_##name(struct vc4_compile *c, struct qreg a, struct qreg b) \
qir_emit(c, qir_inst(QOP_##name, c->undef, a, b)); \
}
#define QIR_PACK(name) \
static inline struct qreg \
qir_##name(struct vc4_compile *c, struct qreg dest, struct qreg a) \
{ \
qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, c->undef)); \
return dest; \
}
QIR_ALU1(MOV)
QIR_ALU2(FADD)
QIR_ALU2(FSUB)
@ -570,12 +597,11 @@ QIR_ALU1(RCP)
QIR_ALU1(RSQ)
QIR_ALU1(EXP2)
QIR_ALU1(LOG2)
QIR_ALU2(PACK_SCALED)
QIR_ALU1(PACK_8888_F)
QIR_ALU2(PACK_8A_F)
QIR_ALU2(PACK_8B_F)
QIR_ALU2(PACK_8C_F)
QIR_ALU2(PACK_8D_F)
QIR_PACK(PACK_8A_F)
QIR_PACK(PACK_8B_F)
QIR_PACK(PACK_8C_F)
QIR_PACK(PACK_8D_F)
QIR_ALU1(VARY_ADD_C)
QIR_NODST_2(TEX_S)
QIR_NODST_2(TEX_T)
@ -627,11 +653,12 @@ qir_UNPACK_16_I(struct vc4_compile *c, struct qreg src, int i)
}
static inline struct qreg
qir_PACK_8_F(struct vc4_compile *c, struct qreg rest, struct qreg val, int chan)
qir_PACK_8_F(struct vc4_compile *c, struct qreg dest, struct qreg val, int chan)
{
struct qreg t = qir_get_temp(c);
qir_emit(c, qir_inst(QOP_PACK_8A_F + chan, t, rest, val));
return t;
qir_emit(c, qir_inst(QOP_PACK_8A_F + chan, dest, val, c->undef));
if (dest.file == QFILE_TEMP)
c->defs[dest.index] = NULL;
return dest;
}
static inline struct qreg

7
src/gallium/drivers/vc4/vc4_qpu.h
View file

@ -24,6 +24,7 @@
#ifndef VC4_QPU_H
#define VC4_QPU_H
#include <stdio.h>
#include <stdint.h>
#include "util/u_math.h"
@ -205,6 +206,12 @@ M_ALU2(V8SUBS)
void
vc4_qpu_disasm(const uint64_t *instructions, int num_instructions);
void
vc4_qpu_disasm_pack_mul(FILE *out, uint32_t pack);
void
vc4_qpu_disasm_pack_a(FILE *out, uint32_t pack);
void
vc4_qpu_validate(uint64_t *insts, uint32_t num_inst);

16
src/gallium/drivers/vc4/vc4_qpu_disasm.c
View file

@ -245,6 +245,18 @@ get_special_write_desc(int reg, bool is_a)
return special_write[reg];
}
void
vc4_qpu_disasm_pack_mul(FILE *out, uint32_t pack)
{
fprintf(out, ".%s", DESC(qpu_pack_mul, pack));
}
void
vc4_qpu_disasm_pack_a(FILE *out, uint32_t pack)
{
fprintf(out, "%s", DESC(qpu_pack_a, pack));
}
static void
print_alu_dst(uint64_t inst, bool is_mul)
{
@ -263,9 +275,9 @@ print_alu_dst(uint64_t inst, bool is_mul)
fprintf(stderr, "%s%d?", file, waddr);
if (is_mul && (inst & QPU_PM)) {
fprintf(stderr, ".%s", DESC(qpu_pack_mul, pack));
vc4_qpu_disasm_pack_mul(stderr, pack);
} else if (is_a && !(inst & QPU_PM)) {
fprintf(stderr, "%s", DESC(qpu_pack_a, pack));
vc4_qpu_disasm_pack_a(stderr, pack);
}
}

63
src/gallium/drivers/vc4/vc4_qpu_emit.c
View file

@ -179,10 +179,9 @@ vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c)
static const struct {
uint32_t op;
bool is_mul;
} translate[] = {
#define A(name) [QOP_##name] = {QPU_A_##name, false}
#define M(name) [QOP_##name] = {QPU_M_##name, true}
#define A(name) [QOP_##name] = {QPU_A_##name}
#define M(name) [QOP_##name] = {QPU_M_##name}
A(FADD),
A(FSUB),
A(FMIN),
@ -336,28 +335,12 @@ vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c)
case QOP_PACK_8B_F:
case QOP_PACK_8C_F:
case QOP_PACK_8D_F:
/* If dst doesn't happen to already contain src[0],
* then we have to move it in.
*/
if (qinst->src[0].file != QFILE_NULL &&
(src[0].mux != dst.mux || src[0].addr != dst.addr)) {
/* Don't overwrite src1 while setting up
* the dst!
*/
if (dst.mux == src[1].mux &&
dst.addr == src[1].addr) {
queue(c, qpu_m_MOV(qpu_rb(31), src[1]));
src[1] = qpu_rb(31);
}
queue(c, qpu_m_MOV(dst, src[0]));
}
queue(c, qpu_m_MOV(dst, src[1]));
*last_inst(c) |= QPU_PM;
*last_inst(c) |= QPU_SET_FIELD(QPU_PACK_MUL_8A +
qinst->op - QOP_PACK_8A_F,
QPU_PACK);
queue(c,
qpu_m_MOV(dst, src[0]) |
QPU_PM |
QPU_SET_FIELD(QPU_PACK_MUL_8A +
qinst->op - QOP_PACK_8A_F,
QPU_PACK));
break;
case QOP_FRAG_X:
@ -419,24 +402,6 @@ vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c)
queue(c, qpu_a_FADD(dst, src[0], qpu_r5()));
break;
case QOP_PACK_SCALED: {
uint64_t a = (qpu_a_MOV(dst, src[0]) |
QPU_SET_FIELD(QPU_PACK_A_16A,
QPU_PACK));
uint64_t b = (qpu_a_MOV(dst, src[1]) |
QPU_SET_FIELD(QPU_PACK_A_16B,
QPU_PACK));
if (dst.mux == src[1].mux && dst.addr == src[1].addr) {
queue(c, b);
queue(c, a);
} else {
queue(c, a);
queue(c, b);
}
break;
}
case QOP_TEX_S:
case QOP_TEX_T:
case QOP_TEX_R:
@ -529,14 +494,24 @@ vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c)
fixup_raddr_conflict(c, dst, &src[0], &src[1]);
if (translate[qinst->op].is_mul) {
if (qir_is_mul(qinst)) {
queue(c, qpu_m_alu2(translate[qinst->op].op,
dst,
src[0], src[1]));
if (qinst->dst.pack) {
*last_inst(c) |= QPU_PM;
*last_inst(c) |= QPU_SET_FIELD(qinst->dst.pack,
QPU_PACK);
}
} else {
queue(c, qpu_a_alu2(translate[qinst->op].op,
dst,
src[0], src[1]));
if (qinst->dst.pack) {
assert(dst.mux == QPU_MUX_A);
*last_inst(c) |= QPU_SET_FIELD(qinst->dst.pack,
QPU_PACK);
}
}
break;

42
src/gallium/drivers/vc4/vc4_register_allocate.c
View file

@ -113,9 +113,10 @@ vc4_alloc_reg_set(struct vc4_context *vc4)
if (vc4->regs)
return;
vc4->regs = ra_alloc_reg_set(vc4, ARRAY_SIZE(vc4_regs));
vc4->regs = ra_alloc_reg_set(vc4, ARRAY_SIZE(vc4_regs), true);
vc4->reg_class_any = ra_alloc_reg_class(vc4->regs);
vc4->reg_class_a_or_b_or_acc = ra_alloc_reg_class(vc4->regs);
vc4->reg_class_r4_or_a = ra_alloc_reg_class(vc4->regs);
vc4->reg_class_a = ra_alloc_reg_class(vc4->regs);
for (uint32_t i = 0; i < ARRAY_SIZE(vc4_regs); i++) {
@ -130,10 +131,12 @@ vc4_alloc_reg_set(struct vc4_context *vc4)
*/
if (vc4_regs[i].mux == QPU_MUX_R4) {
ra_class_add_reg(vc4->regs, vc4->reg_class_r4_or_a, i);
ra_class_add_reg(vc4->regs, vc4->reg_class_any, i);
continue;
}
ra_class_add_reg(vc4->regs, vc4->reg_class_any, i);
ra_class_add_reg(vc4->regs, vc4->reg_class_a_or_b_or_acc, i);
}
for (uint32_t i = AB_INDEX; i < AB_INDEX + 64; i += 2) {
@ -177,7 +180,8 @@ vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c)
uint8_t class_bits[c->num_temps];
struct qpu_reg *temp_registers = calloc(c->num_temps,
sizeof(*temp_registers));
memset(def, 0, sizeof(def));
for (int i = 0; i < ARRAY_SIZE(def); i++)
def[i] = ~0;
memset(use, 0, sizeof(use));
/* If things aren't ever written (undefined values), just read from
@ -196,7 +200,7 @@ vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c)
uint32_t ip = 0;
list_for_each_entry(struct qinst, inst, &c->instructions, link) {
if (inst->dst.file == QFILE_TEMP) {
def[inst->dst.index] = ip;
def[inst->dst.index] = MIN2(ip, def[inst->dst.index]);
use[inst->dst.index] = ip;
}
@ -267,17 +271,33 @@ vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c)
AB_INDEX + QPU_R_FRAG_PAYLOAD_ZW * 2);
break;
case QOP_PACK_SCALED:
/* The pack flags require an A-file dst register. */
class_bits[inst->dst.index] &= CLASS_BIT_A;
break;
default:
break;
}
if (inst->dst.pack && !qir_is_mul(inst)) {
/* The non-MUL pack flags require an A-file dst
* register.
*/
class_bits[inst->dst.index] &= CLASS_BIT_A;
}
if (qir_src_needs_a_file(inst)) {
class_bits[inst->src[0].index] &= CLASS_BIT_A;
switch (inst->op) {
case QOP_UNPACK_8A_F:
case QOP_UNPACK_8B_F:
case QOP_UNPACK_8C_F:
case QOP_UNPACK_8D_F:
/* Special case: these can be done as R4
* unpacks, as well.
*/
class_bits[inst->src[0].index] &= (CLASS_BIT_A |
CLASS_BIT_R4);
break;
default:
class_bits[inst->src[0].index] &= CLASS_BIT_A;
break;
}
}
ip++;
}
@ -287,9 +307,11 @@ vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c)
switch (class_bits[i]) {
case CLASS_BIT_A | CLASS_BIT_B_OR_ACC | CLASS_BIT_R4:
case CLASS_BIT_A | CLASS_BIT_B_OR_ACC:
ra_set_node_class(g, node, vc4->reg_class_any);
break;
case CLASS_BIT_A | CLASS_BIT_B_OR_ACC:
ra_set_node_class(g, node, vc4->reg_class_a_or_b_or_acc);
break;
case CLASS_BIT_A | CLASS_BIT_R4:
ra_set_node_class(g, node, vc4->reg_class_r4_or_a);
break;

1
src/gallium/include/pipe/p_state.h
View file

@ -663,6 +663,7 @@ struct pipe_blit_info
boolean render_condition_enable; /**< whether the blit should honor the
current render condition */
boolean alpha_blend; /* dst.rgb = src.rgb * src.a + dst.rgb * (1 - src.a) */
};

33
src/gallium/state_trackers/clover/llvm/invocation.cpp
View file

@ -346,6 +346,15 @@ namespace {
// Kernel metadata
struct kernel_arg_md {
llvm::StringRef type_name;
llvm::StringRef access_qual;
kernel_arg_md(llvm::StringRef type_name_, llvm::StringRef access_qual_):
type_name(type_name_), access_qual(access_qual_) {}
};
#if HAVE_LLVM >= 0x0306
const llvm::MDNode *
get_kernel_metadata(const llvm::Function *kernel_func) {
auto mod = kernel_func->getParent();
@ -356,12 +365,8 @@ namespace {
const llvm::MDNode *kernel_node = nullptr;
for (unsigned i = 0; i < kernels_node->getNumOperands(); ++i) {
#if HAVE_LLVM >= 0x0306
auto func = llvm::mdconst::dyn_extract<llvm::Function>(
#else
auto func = llvm::dyn_cast<llvm::Function>(
#endif
kernels_node->getOperand(i)->getOperand(0));
kernels_node->getOperand(i)->getOperand(0));
if (func == kernel_func) {
kernel_node = kernels_node->getOperand(i);
break;
@ -387,13 +392,6 @@ namespace {
return node;
}
struct kernel_arg_md {
llvm::StringRef type_name;
llvm::StringRef access_qual;
kernel_arg_md(llvm::StringRef type_name_, llvm::StringRef access_qual_):
type_name(type_name_), access_qual(access_qual_) {}
};
std::vector<kernel_arg_md>
get_kernel_arg_md(const llvm::Function *kernel_func) {
auto num_args = kernel_func->getArgumentList().size();
@ -415,6 +413,17 @@ namespace {
return res;
}
#else
std::vector<kernel_arg_md>
get_kernel_arg_md(const llvm::Function *kernel_func) {
return std::vector<kernel_arg_md>(
kernel_func->getArgumentList().size(),
kernel_arg_md("", ""));
}
#endif // HAVE_LLVM >= 0x0306
std::vector<module::argument>
get_kernel_args(const llvm::Module *mod, const std::string &kernel_name,
const clang::LangAS::Map &address_spaces) {

38
src/gallium/state_trackers/nine/adapter9.c
View file

@ -545,7 +545,7 @@ NineAdapter9_GetDeviceCaps( struct NineAdapter9 *This,
/*D3DDEVCAPS_RTPATCHES |*/
/*D3DDEVCAPS_RTPATCHHANDLEZERO |*/
/*D3DDEVCAPS_SEPARATETEXTUREMEMORIES |*/
/*D3DDEVCAPS_TEXTURENONLOCALVIDMEM |*/
D3DDEVCAPS_TEXTURENONLOCALVIDMEM |
/* D3DDEVCAPS_TEXTURESYSTEMMEMORY |*/
D3DDEVCAPS_TEXTUREVIDEOMEMORY |
D3DDEVCAPS_TLVERTEXSYSTEMMEMORY |
@ -561,32 +561,32 @@ NineAdapter9_GetDeviceCaps( struct NineAdapter9 *This,
D3DPMISCCAPS_TSSARGTEMP |
D3DPMISCCAPS_BLENDOP |
D3DPIPECAP(INDEP_BLEND_ENABLE, D3DPMISCCAPS_INDEPENDENTWRITEMASKS) |
/*D3DPMISCCAPS_PERSTAGECONSTANT |*/
/*D3DPMISCCAPS_PERSTAGECONSTANT |*/ /* TODO */
/*D3DPMISCCAPS_POSTBLENDSRGBCONVERT |*/ /* TODO */
D3DPMISCCAPS_FOGANDSPECULARALPHA |
D3DPIPECAP(BLEND_EQUATION_SEPARATE, D3DPMISCCAPS_SEPARATEALPHABLEND) |
D3DPIPECAP(MIXED_COLORBUFFER_FORMATS, D3DPMISCCAPS_MRTINDEPENDENTBITDEPTHS) |
D3DPMISCCAPS_MRTPOSTPIXELSHADERBLENDING |
/*D3DPMISCCAPS_FOGVERTEXCLAMPED*/0;
D3DPMISCCAPS_FOGVERTEXCLAMPED;
if (!screen->get_param(screen, PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION))
pCaps->PrimitiveMiscCaps |= D3DPMISCCAPS_CLIPTLVERTS;
pCaps->RasterCaps =
D3DPIPECAP(ANISOTROPIC_FILTER, D3DPRASTERCAPS_ANISOTROPY) |
/*D3DPRASTERCAPS_COLORPERSPECTIVE |*/
D3DPRASTERCAPS_COLORPERSPECTIVE |
D3DPRASTERCAPS_DITHER |
D3DPRASTERCAPS_DEPTHBIAS |
/*D3DPRASTERCAPS_FOGRANGE |*/
/*D3DPRASTERCAPS_FOGTABLE |*/
/*D3DPRASTERCAPS_FOGVERTEX |*/
D3DPRASTERCAPS_FOGRANGE |
D3DPRASTERCAPS_FOGTABLE |
D3DPRASTERCAPS_FOGVERTEX |
D3DPRASTERCAPS_MIPMAPLODBIAS |
D3DPRASTERCAPS_MULTISAMPLE_TOGGLE |
D3DPRASTERCAPS_SCISSORTEST |
D3DPRASTERCAPS_SLOPESCALEDEPTHBIAS |
/*D3DPRASTERCAPS_WBUFFER |*/
/*D3DPRASTERCAPS_WFOG |*/
D3DPRASTERCAPS_WFOG |
/*D3DPRASTERCAPS_ZBUFFERLESSHSR |*/
/*D3DPRASTERCAPS_ZFOG |*/
D3DPRASTERCAPS_ZFOG |
D3DPRASTERCAPS_ZTEST;
pCaps->ZCmpCaps = D3DPCMPCAPS_NEVER |
@ -697,15 +697,12 @@ NineAdapter9_GetDeviceCaps( struct NineAdapter9 *This,
pCaps->MaxAnisotropy =
(DWORD)screen->get_paramf(screen, PIPE_CAPF_MAX_TEXTURE_ANISOTROPY);
pCaps->MaxVertexW = 1.0f; /* XXX */
pCaps->GuardBandLeft = screen->get_paramf(screen,
PIPE_CAPF_GUARD_BAND_LEFT);
pCaps->GuardBandTop = screen->get_paramf(screen,
PIPE_CAPF_GUARD_BAND_TOP);
pCaps->GuardBandRight = screen->get_paramf(screen,
PIPE_CAPF_GUARD_BAND_RIGHT);
pCaps->GuardBandBottom = screen->get_paramf(screen,
PIPE_CAPF_GUARD_BAND_BOTTOM);
/* Values for GeForce 9600 GT */
pCaps->MaxVertexW = 1e10f;
pCaps->GuardBandLeft = -1e9f;
pCaps->GuardBandTop = -1e9f;
pCaps->GuardBandRight = 1e9f;
pCaps->GuardBandBottom = 1e9f;
pCaps->ExtentsAdjust = 0.0f;
pCaps->StencilCaps =
@ -724,8 +721,6 @@ NineAdapter9_GetDeviceCaps( struct NineAdapter9 *This,
/*D3DFVFCAPS_DONOTSTRIPELEMENTS |*/
D3DFVFCAPS_PSIZE;
/* XXX: Some of these are probably not in SM2.0 so cap them when I figure
* them out. For now leave them all enabled. */
pCaps->TextureOpCaps = D3DTEXOPCAPS_DISABLE |
D3DTEXOPCAPS_SELECTARG1 |
D3DTEXOPCAPS_SELECTARG2 |
@ -796,7 +791,8 @@ NineAdapter9_GetDeviceCaps( struct NineAdapter9 *This,
pCaps->MaxVertexShaderConst = NINE_MAX_CONST_F;
pCaps->PixelShaderVersion = D3DPS_VERSION(3,0);
pCaps->PixelShader1xMaxValue = 8.0f; /* XXX: wine */
/* Value for GeForce 9600 GT */
pCaps->PixelShader1xMaxValue = 65504.f;
pCaps->DevCaps2 = D3DDEVCAPS2_STREAMOFFSET |
D3DDEVCAPS2_VERTEXELEMENTSCANSHARESTREAMOFFSET |

46
src/gallium/state_trackers/nine/basetexture9.c
View file

@ -57,7 +57,8 @@ NineBaseTexture9_ctor( struct NineBaseTexture9 *This,
user_assert(!(Usage & (D3DUSAGE_RENDERTARGET | D3DUSAGE_DEPTHSTENCIL)) ||
Pool == D3DPOOL_DEFAULT, D3DERR_INVALIDCALL);
user_assert(!(Usage & D3DUSAGE_DYNAMIC) ||
Pool != D3DPOOL_MANAGED, D3DERR_INVALIDCALL);
!(Pool == D3DPOOL_MANAGED ||
Pool == D3DPOOL_SCRATCH), D3DERR_INVALIDCALL);
hr = NineResource9_ctor(&This->base, pParams, initResource, alloc, Type, Pool, Usage);
if (FAILED(hr))
@ -85,6 +86,9 @@ NineBaseTexture9_ctor( struct NineBaseTexture9 *This,
util_format_has_depth(util_format_description(This->base.info.format));
list_inithead(&This->list);
list_inithead(&This->list2);
if (Pool == D3DPOOL_MANAGED)
list_add(&This->list2, &This->base.base.device->managed_textures);
return D3D_OK;
}
@ -98,7 +102,9 @@ NineBaseTexture9_dtor( struct NineBaseTexture9 *This )
pipe_sampler_view_reference(&This->view[1], NULL);
if (This->list.prev != NULL && This->list.next != NULL)
list_del(&This->list),
list_del(&This->list);
if (This->list2.prev != NULL && This->list2.next != NULL)
list_del(&This->list2);
NineResource9_dtor(&This->base);
}
@ -153,6 +159,8 @@ NineBaseTexture9_SetAutoGenFilterType( struct NineBaseTexture9 *This,
user_assert(FilterType != D3DTEXF_NONE, D3DERR_INVALIDCALL);
This->mipfilter = FilterType;
This->dirty_mip = TRUE;
NineBaseTexture9_GenerateMipSubLevels(This);
return D3D_OK;
}
@ -310,14 +318,12 @@ NineBaseTexture9_UploadSelf( struct NineBaseTexture9 *This )
tex->dirty_box.width, tex->dirty_box.height, tex->dirty_box.depth);
if (tex->dirty_box.width) {
for (l = 0; l <= last_level; ++l) {
for (l = min_level_dirty; l <= last_level; ++l) {
u_box_minify_2d(&box, &tex->dirty_box, l);
NineVolume9_AddDirtyRegion(tex->volumes[l], &tex->dirty_box);
NineVolume9_UploadSelf(tex->volumes[l], &box);
}
memset(&tex->dirty_box, 0, sizeof(tex->dirty_box));
}
for (l = min_level_dirty; l <= last_level; ++l)
NineVolume9_UploadSelf(tex->volumes[l]);
} else {
assert(!"invalid texture type");
}
@ -361,8 +367,7 @@ NineBaseTexture9_UploadSelf( struct NineBaseTexture9 *This )
box.width = u_minify(This->base.info.width0, l);
box.height = u_minify(This->base.info.height0, l);
box.depth = u_minify(This->base.info.depth0, l);
NineVolume9_AddDirtyRegion(tex->volumes[l], &box);
NineVolume9_UploadSelf(tex->volumes[l]);
NineVolume9_UploadSelf(tex->volumes[l], &box);
}
} else {
assert(!"invalid texture type");
@ -381,8 +386,7 @@ NineBaseTexture9_UploadSelf( struct NineBaseTexture9 *This )
void WINAPI
NineBaseTexture9_GenerateMipSubLevels( struct NineBaseTexture9 *This )
{
struct pipe_resource *resource = This->base.resource;
struct pipe_resource *resource;
unsigned base_level = 0;
unsigned last_level = This->base.info.last_level - This->managed.lod;
unsigned first_layer = 0;
@ -405,6 +409,8 @@ NineBaseTexture9_GenerateMipSubLevels( struct NineBaseTexture9 *This )
last_layer = util_max_layer(This->view[0]->texture, base_level);
resource = This->base.resource;
util_gen_mipmap(This->pipe, resource,
resource->format, base_level, last_level,
first_layer, last_layer, filter);
@ -530,6 +536,11 @@ NineBaseTexture9_UpdateSamplerView( struct NineBaseTexture9 *This,
swizzle[2] = PIPE_SWIZZLE_RED;
swizzle[3] = PIPE_SWIZZLE_RED;
}
} else if (resource->format == PIPE_FORMAT_RGTC2_UNORM) {
swizzle[0] = PIPE_SWIZZLE_GREEN;
swizzle[1] = PIPE_SWIZZLE_RED;
swizzle[2] = PIPE_SWIZZLE_ONE;
swizzle[3] = PIPE_SWIZZLE_ONE;
} else if (resource->format != PIPE_FORMAT_A8_UNORM &&
resource->format != PIPE_FORMAT_RGTC1_UNORM) {
/* exceptions:
@ -578,6 +589,21 @@ NineBaseTexture9_PreLoad( struct NineBaseTexture9 *This )
NineBaseTexture9_UploadSelf(This);
}
void
NineBaseTexture9_UnLoad( struct NineBaseTexture9 *This )
{
if (This->base.pool != D3DPOOL_MANAGED ||
This->managed.lod_resident == -1)
return;
pipe_resource_reference(&This->base.resource, NULL);
This->managed.lod_resident = -1;
This->managed.dirty = TRUE;
/* If the texture is bound, we have to re-upload it */
BASETEX_REGISTER_UPDATE(This);
}
#ifdef DEBUG
void
NineBaseTexture9_Dump( struct NineBaseTexture9 *This )

6
src/gallium/state_trackers/nine/basetexture9.h
View file

@ -30,7 +30,8 @@
struct NineBaseTexture9
{
struct NineResource9 base;
struct list_head list;
struct list_head list; /* for update_textures */
struct list_head list2; /* for managed_textures */
/* g3d */
struct pipe_context *pipe;
@ -94,6 +95,9 @@ NineBaseTexture9_GenerateMipSubLevels( struct NineBaseTexture9 *This );
void WINAPI
NineBaseTexture9_PreLoad( struct NineBaseTexture9 *This );
void
NineBaseTexture9_UnLoad( struct NineBaseTexture9 *This );
/* For D3DPOOL_MANAGED only (after SetLOD change): */
HRESULT
NineBaseTexture9_CreatePipeResource( struct NineBaseTexture9 *This,

27
src/gallium/state_trackers/nine/cubetexture9.c
View file

@ -43,7 +43,7 @@ NineCubeTexture9_ctor( struct NineCubeTexture9 *This,
struct pipe_screen *screen = pParams->device->screen;
enum pipe_format pf;
unsigned i, l, f, offset, face_size = 0;
unsigned *level_offsets;
unsigned *level_offsets = NULL;
D3DSURFACE_DESC sfdesc;
void *p;
HRESULT hr;
@ -70,6 +70,13 @@ NineCubeTexture9_ctor( struct NineCubeTexture9 *This,
if (Format == D3DFMT_ATI1 || Format == D3DFMT_ATI2)
return D3DERR_INVALIDCALL;
if (compressed_format(Format)) {
const unsigned w = util_format_get_blockwidth(pf);
const unsigned h = util_format_get_blockheight(pf);
user_assert(!(EdgeLength % w) && !(EdgeLength % h), D3DERR_INVALIDCALL);
}
info->screen = pParams->device->screen;
info->target = PIPE_TEXTURE_CUBE;
info->format = pf;
@ -106,7 +113,7 @@ NineCubeTexture9_ctor( struct NineCubeTexture9 *This,
face_size = nine_format_get_size_and_offsets(pf, level_offsets,
EdgeLength, EdgeLength,
info->last_level);
This->managed_buffer = MALLOC(6 * face_size);
This->managed_buffer = align_malloc(6 * face_size, 32);
if (!This->managed_buffer)
return E_OUTOFMEMORY;
}
@ -150,8 +157,12 @@ NineCubeTexture9_ctor( struct NineCubeTexture9 *This,
}
}
for (i = 0; i < 6; ++i) /* width = 0 means empty, depth stays 1 */
for (i = 0; i < 6; ++i) {
/* Textures start initially dirty */
This->dirty_rect[i].width = EdgeLength;
This->dirty_rect[i].height = EdgeLength;
This->dirty_rect[i].depth = 1;
}
return D3D_OK;
}
@ -259,13 +270,17 @@ NineCubeTexture9_AddDirtyRect( struct NineCubeTexture9 *This,
user_assert(FaceType < 6, D3DERR_INVALIDCALL);
if (This->base.base.pool != D3DPOOL_MANAGED) {
if (This->base.base.usage & D3DUSAGE_AUTOGENMIPMAP)
if (This->base.base.usage & D3DUSAGE_AUTOGENMIPMAP) {
This->base.dirty_mip = TRUE;
BASETEX_REGISTER_UPDATE(&This->base);
}
return D3D_OK;
}
This->base.managed.dirty = TRUE;
BASETEX_REGISTER_UPDATE(&This->base);
if (This->base.base.pool == D3DPOOL_MANAGED) {
This->base.managed.dirty = TRUE;
BASETEX_REGISTER_UPDATE(&This->base);
}
if (!pDirtyRect) {
u_box_origin_2d(This->base.base.info.width0,

436
src/gallium/state_trackers/nine/device9.c
View file

@ -119,48 +119,6 @@ NineDevice9_SetDefaultState( struct NineDevice9 *This, boolean is_reset )
This, (IDirect3DSurface9 *)This->swapchains[0]->zsbuf);
}
void
NineDevice9_RestoreNonCSOState( struct NineDevice9 *This, unsigned mask )
{
struct pipe_context *pipe = This->pipe;
DBG("This=%p mask=%u\n", This, mask);
if (mask & 0x1) {
struct pipe_constant_buffer cb;
cb.buffer_offset = 0;
if (This->prefer_user_constbuf) {
cb.buffer = NULL;
cb.user_buffer = This->state.vs_const_f;
} else {
cb.buffer = This->constbuf_vs;
cb.user_buffer = NULL;
}
cb.buffer_size = This->vs_const_size;
pipe->set_constant_buffer(pipe, PIPE_SHADER_VERTEX, 0, &cb);
if (This->prefer_user_constbuf) {
cb.user_buffer = This->state.ps_const_f;
} else {
cb.buffer = This->constbuf_ps;
}
cb.buffer_size = This->ps_const_size;
pipe->set_constant_buffer(pipe, PIPE_SHADER_FRAGMENT, 0, &cb);
}
if (mask & 0x2) {
struct pipe_poly_stipple stipple;
memset(&stipple, ~0, sizeof(stipple));
pipe->set_polygon_stipple(pipe, &stipple);
}
This->state.changed.group = NINE_STATE_ALL;
This->state.changed.vtxbuf = (1ULL << This->caps.MaxStreams) - 1;
This->state.changed.ucp = (1 << PIPE_MAX_CLIP_PLANES) - 1;
This->state.changed.texture = NINE_PS_SAMPLERS_MASK | NINE_VS_SAMPLERS_MASK;
}
#define GET_PCAP(n) pScreen->get_param(pScreen, PIPE_CAP_##n)
HRESULT
NineDevice9_ctor( struct NineDevice9 *This,
@ -186,6 +144,7 @@ NineDevice9_ctor( struct NineDevice9 *This,
if (FAILED(hr)) { return hr; }
list_inithead(&This->update_textures);
list_inithead(&This->managed_textures);
This->screen = pScreen;
This->caps = *pCaps;
@ -341,16 +300,19 @@ NineDevice9_ctor( struct NineDevice9 *This,
This->state.vs_const_f = CALLOC(This->vs_const_size, 1);
This->state.ps_const_f = CALLOC(This->ps_const_size, 1);
This->state.vs_lconstf_temp = CALLOC(This->vs_const_size,1);
This->state.ps_lconstf_temp = CALLOC(This->ps_const_size,1);
if (!This->state.vs_const_f || !This->state.ps_const_f ||
!This->state.vs_lconstf_temp)
!This->state.vs_lconstf_temp || !This->state.ps_lconstf_temp)
return E_OUTOFMEMORY;
if (strstr(pScreen->get_name(pScreen), "AMD") ||
strstr(pScreen->get_name(pScreen), "ATI")) {
This->prefer_user_constbuf = TRUE;
This->driver_bugs.buggy_barycentrics = TRUE;
}
/* Disable NV path for now, needs some fixes */
This->prefer_user_constbuf = TRUE;
tmpl.target = PIPE_BUFFER;
tmpl.format = PIPE_FORMAT_R8_UNORM;
tmpl.height0 = 1;
@ -376,6 +338,8 @@ NineDevice9_ctor( struct NineDevice9 *This,
{
struct pipe_resource tmplt;
struct pipe_sampler_view templ;
struct pipe_sampler_state samp;
memset(&samp, 0, sizeof(samp));
tmplt.target = PIPE_TEXTURE_2D;
tmplt.width0 = 1;
@ -404,22 +368,39 @@ NineDevice9_ctor( struct NineDevice9 *This,
templ.swizzle_a = PIPE_SWIZZLE_ONE;
templ.target = This->dummy_texture->target;
This->dummy_sampler = This->pipe->create_sampler_view(This->pipe, This->dummy_texture, &templ);
if (!This->dummy_sampler)
This->dummy_sampler_view = This->pipe->create_sampler_view(This->pipe, This->dummy_texture, &templ);
if (!This->dummy_sampler_view)
return D3DERR_DRIVERINTERNALERROR;
samp.min_mip_filter = PIPE_TEX_MIPFILTER_NONE;
samp.max_lod = 15.0f;
samp.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
samp.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
samp.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
samp.min_img_filter = PIPE_TEX_FILTER_NEAREST;
samp.mag_img_filter = PIPE_TEX_FILTER_NEAREST;
samp.compare_mode = PIPE_TEX_COMPARE_NONE;
samp.compare_func = PIPE_FUNC_LEQUAL;
samp.normalized_coords = 1;
samp.seamless_cube_map = 1;
This->dummy_sampler_state = samp;
}
/* Allocate upload helper for drivers that suck (from st pov ;). */
{
unsigned bind = 0;
This->driver_caps.user_vbufs = GET_PCAP(USER_VERTEX_BUFFERS);
This->driver_caps.user_ibufs = GET_PCAP(USER_INDEX_BUFFERS);
This->driver_caps.user_vbufs = GET_PCAP(USER_VERTEX_BUFFERS);
This->driver_caps.user_ibufs = GET_PCAP(USER_INDEX_BUFFERS);
This->driver_caps.user_cbufs = GET_PCAP(USER_CONSTANT_BUFFERS);
if (!This->driver_caps.user_vbufs) bind |= PIPE_BIND_VERTEX_BUFFER;
if (!This->driver_caps.user_ibufs) bind |= PIPE_BIND_INDEX_BUFFER;
if (bind)
This->upload = u_upload_create(This->pipe, 1 << 20, 4, bind);
if (!This->driver_caps.user_vbufs)
This->vertex_uploader = u_upload_create(This->pipe, 65536, 4, PIPE_BIND_VERTEX_BUFFER);
if (!This->driver_caps.user_ibufs)
This->index_uploader = u_upload_create(This->pipe, 128 * 1024, 4, PIPE_BIND_INDEX_BUFFER);
if (!This->driver_caps.user_cbufs) {
unsigned alignment = GET_PCAP(CONSTANT_BUFFER_OFFSET_ALIGNMENT);
This->constbuf_uploader = u_upload_create(This->pipe, This->vs_const_size,
alignment, PIPE_BIND_CONSTANT_BUFFER);
}
This->driver_caps.window_space_position_support = GET_PCAP(TGSI_VS_WINDOW_SPACE_POSITION);
@ -429,10 +410,15 @@ NineDevice9_ctor( struct NineDevice9 *This,
nine_ff_init(This); /* initialize fixed function code */
NineDevice9_SetDefaultState(This, FALSE);
NineDevice9_RestoreNonCSOState(This, ~0);
{
struct pipe_poly_stipple stipple;
memset(&stipple, ~0, sizeof(stipple));
This->pipe->set_polygon_stipple(This->pipe, &stipple);
}
This->update = &This->state;
nine_update_state(This, ~0);
nine_update_state(This);
ID3DPresentGroup_Release(This->present);
@ -452,12 +438,16 @@ NineDevice9_dtor( struct NineDevice9 *This )
nine_ff_fini(This);
nine_state_clear(&This->state, TRUE);
if (This->upload)
u_upload_destroy(This->upload);
if (This->vertex_uploader)
u_upload_destroy(This->vertex_uploader);
if (This->index_uploader)
u_upload_destroy(This->index_uploader);
if (This->constbuf_uploader)
u_upload_destroy(This->constbuf_uploader);
nine_bind(&This->record, NULL);
pipe_sampler_view_reference(&This->dummy_sampler, NULL);
pipe_sampler_view_reference(&This->dummy_sampler_view, NULL);
pipe_resource_reference(&This->dummy_texture, NULL);
pipe_resource_reference(&This->constbuf_vs, NULL);
pipe_resource_reference(&This->constbuf_ps, NULL);
@ -465,6 +455,7 @@ NineDevice9_dtor( struct NineDevice9 *This )
FREE(This->state.vs_const_f);
FREE(This->state.ps_const_f);
FREE(This->state.vs_lconstf_temp);
FREE(This->state.ps_lconstf_temp);
if (This->swapchains) {
for (i = 0; i < This->nswapchains; ++i)
@ -547,10 +538,14 @@ NineDevice9_GetAvailableTextureMem( struct NineDevice9 *This )
HRESULT WINAPI
NineDevice9_EvictManagedResources( struct NineDevice9 *This )
{
/* We don't really need to do anything here, but might want to free up
* the GPU virtual address space by killing pipe_resources.
*/
STUB(D3D_OK);
struct NineBaseTexture9 *tex;
DBG("This=%p\n", This);
LIST_FOR_EACH_ENTRY(tex, &This->managed_textures, list2) {
NineBaseTexture9_UnLoad(tex);
}
return D3D_OK;
}
HRESULT WINAPI
@ -599,11 +594,11 @@ NineDevice9_SetCursorProperties( struct NineDevice9 *This,
UINT YHotSpot,
IDirect3DSurface9 *pCursorBitmap )
{
/* TODO: hardware cursor */
struct NineSurface9 *surf = NineSurface9(pCursorBitmap);
struct pipe_context *pipe = This->pipe;
struct pipe_box box;
struct pipe_transfer *transfer;
BOOL hw_cursor;
void *ptr;
DBG_FLAG(DBG_SWAPCHAIN, "This=%p XHotSpot=%u YHotSpot=%u "
@ -611,8 +606,15 @@ NineDevice9_SetCursorProperties( struct NineDevice9 *This,
user_assert(pCursorBitmap, D3DERR_INVALIDCALL);
This->cursor.w = MIN2(surf->desc.Width, This->cursor.image->width0);
This->cursor.h = MIN2(surf->desc.Height, This->cursor.image->height0);
if (This->swapchains[0]->params.Windowed) {
This->cursor.w = MIN2(surf->desc.Width, 32);
This->cursor.h = MIN2(surf->desc.Height, 32);
hw_cursor = 1; /* always use hw cursor for windowed mode */
} else {
This->cursor.w = MIN2(surf->desc.Width, This->cursor.image->width0);
This->cursor.h = MIN2(surf->desc.Height, This->cursor.image->height0);
hw_cursor = This->cursor.w == 32 && This->cursor.h == 32;
}
u_box_origin_2d(This->cursor.w, This->cursor.h, &box);
@ -643,16 +645,21 @@ NineDevice9_SetCursorProperties( struct NineDevice9 *This,
lock.pBits, lock.Pitch,
This->cursor.w, This->cursor.h);
if (!This->cursor.software &&
This->cursor.w == 32 && This->cursor.h == 32)
ID3DPresent_SetCursor(This->swapchains[0]->present,
lock.pBits, &This->cursor.hotspot,
This->cursor.visible);
if (hw_cursor)
hw_cursor = ID3DPresent_SetCursor(This->swapchains[0]->present,
lock.pBits,
&This->cursor.hotspot,
This->cursor.visible) == D3D_OK;
NineSurface9_UnlockRect(surf);
}
pipe->transfer_unmap(pipe, transfer);
/* hide cursor if we emulate it */
if (!hw_cursor)
ID3DPresent_SetCursor(This->swapchains[0]->present, NULL, NULL, FALSE);
This->cursor.software = !hw_cursor;
return D3D_OK;
}
@ -670,7 +677,7 @@ NineDevice9_SetCursorPosition( struct NineDevice9 *This,
This->cursor.pos.y = Y;
if (!This->cursor.software)
ID3DPresent_SetCursorPos(swap->present, &This->cursor.pos);
This->cursor.software = ID3DPresent_SetCursorPos(swap->present, &This->cursor.pos) != D3D_OK;
}
BOOL WINAPI
@ -683,7 +690,7 @@ NineDevice9_ShowCursor( struct NineDevice9 *This,
This->cursor.visible = bShow && (This->cursor.hotspot.x != -1);
if (!This->cursor.software)
ID3DPresent_SetCursor(This->swapchains[0]->present, NULL, NULL, bShow);
This->cursor.software = ID3DPresent_SetCursor(This->swapchains[0]->present, NULL, NULL, bShow) != D3D_OK;
return old;
}
@ -752,8 +759,8 @@ NineDevice9_Reset( struct NineDevice9 *This,
for (i = 0; i < This->nswapchains; ++i) {
D3DPRESENT_PARAMETERS *params = &pPresentationParameters[i];
hr = NineSwapChain9_Resize(This->swapchains[i], params, NULL);
if (FAILED(hr))
return (hr == D3DERR_OUTOFVIDEOMEMORY) ? hr : D3DERR_DEVICELOST;
if (hr != D3D_OK)
return hr;
}
nine_pipe_context_clear(This);
@ -1108,6 +1115,13 @@ create_zs_or_rt_surface(struct NineDevice9 *This,
default: break;
}
if (compressed_format(Format)) {
const unsigned w = util_format_get_blockwidth(templ.format);
const unsigned h = util_format_get_blockheight(templ.format);
user_assert(!(Width % w) && !(Height % h), D3DERR_INVALIDCALL);
}
if (Pool == D3DPOOL_DEFAULT && Format != D3DFMT_NULL) {
/* resource_create doesn't return an error code, so check format here */
user_assert(templ.format != PIPE_FORMAT_NONE, D3DERR_INVALIDCALL);
@ -1173,6 +1187,8 @@ NineDevice9_UpdateSurface( struct NineDevice9 *This,
{
struct NineSurface9 *dst = NineSurface9(pDestinationSurface);
struct NineSurface9 *src = NineSurface9(pSourceSurface);
int copy_width, copy_height;
RECT destRect;
DBG("This=%p pSourceSurface=%p pDestinationSurface=%p "
"pSourceRect=%p pDestPoint=%p\n", This,
@ -1184,13 +1200,75 @@ NineDevice9_UpdateSurface( struct NineDevice9 *This,
if (pDestPoint)
DBG("pDestPoint = (%u,%u)\n", pDestPoint->x, pDestPoint->y);
user_assert(dst && src, D3DERR_INVALIDCALL);
user_assert(dst->base.pool == D3DPOOL_DEFAULT, D3DERR_INVALIDCALL);
user_assert(src->base.pool == D3DPOOL_SYSTEMMEM, D3DERR_INVALIDCALL);
user_assert(dst->desc.MultiSampleType == D3DMULTISAMPLE_NONE, D3DERR_INVALIDCALL);
user_assert(src->desc.MultiSampleType == D3DMULTISAMPLE_NONE, D3DERR_INVALIDCALL);
return NineSurface9_CopySurface(dst, src, pDestPoint, pSourceRect);
user_assert(!src->lock_count, D3DERR_INVALIDCALL);
user_assert(!dst->lock_count, D3DERR_INVALIDCALL);
user_assert(dst->desc.Format == src->desc.Format, D3DERR_INVALIDCALL);
user_assert(!depth_stencil_format(dst->desc.Format), D3DERR_INVALIDCALL);
if (pSourceRect) {
copy_width = pSourceRect->right - pSourceRect->left;
copy_height = pSourceRect->bottom - pSourceRect->top;
user_assert(pSourceRect->left >= 0 &&
copy_width > 0 &&
pSourceRect->right <= src->desc.Width &&
pSourceRect->top >= 0 &&
copy_height > 0 &&
pSourceRect->bottom <= src->desc.Height,
D3DERR_INVALIDCALL);
} else {
copy_width = src->desc.Width;
copy_height = src->desc.Height;
}
destRect.right = copy_width;
destRect.bottom = copy_height;
if (pDestPoint) {
user_assert(pDestPoint->x >= 0 && pDestPoint->y >= 0,
D3DERR_INVALIDCALL);
destRect.right += pDestPoint->x;
destRect.bottom += pDestPoint->y;
}
user_assert(destRect.right <= dst->desc.Width &&
destRect.bottom <= dst->desc.Height,
D3DERR_INVALIDCALL);
if (compressed_format(dst->desc.Format)) {
const unsigned w = util_format_get_blockwidth(dst->base.info.format);
const unsigned h = util_format_get_blockheight(dst->base.info.format);
if (pDestPoint) {
user_assert(!(pDestPoint->x % w) && !(pDestPoint->y % h),
D3DERR_INVALIDCALL);
}
if (pSourceRect) {
user_assert(!(pSourceRect->left % w) && !(pSourceRect->top % h),
D3DERR_INVALIDCALL);
}
if (!(copy_width == src->desc.Width &&
copy_width == dst->desc.Width &&
copy_height == src->desc.Height &&
copy_height == dst->desc.Height)) {
user_assert(!(copy_width % w) && !(copy_height % h),
D3DERR_INVALIDCALL);
}
}
NineSurface9_CopyMemToDefault(dst, src, pDestPoint, pSourceRect);
return D3D_OK;
}
HRESULT WINAPI
@ -1202,6 +1280,7 @@ NineDevice9_UpdateTexture( struct NineDevice9 *This,
struct NineBaseTexture9 *srcb = NineBaseTexture9(pSourceTexture);
unsigned l, m;
unsigned last_level = dstb->base.info.last_level;
RECT rect;
DBG("This=%p pSourceTexture=%p pDestinationTexture=%p\n", This,
pSourceTexture, pDestinationTexture);
@ -1227,10 +1306,6 @@ NineDevice9_UpdateTexture( struct NineDevice9 *This,
user_assert(dstb->base.type == srcb->base.type, D3DERR_INVALIDCALL);
/* TODO: We can restrict the update to the dirty portions of the source.
* Yes, this seems silly, but it's what MSDN says ...
*/
/* Find src level that matches dst level 0: */
user_assert(srcb->base.info.width0 >= dstb->base.info.width0 &&
srcb->base.info.height0 >= dstb->base.info.height0 &&
@ -1254,9 +1329,25 @@ NineDevice9_UpdateTexture( struct NineDevice9 *This,
struct NineTexture9 *dst = NineTexture9(dstb);
struct NineTexture9 *src = NineTexture9(srcb);
for (l = 0; l <= last_level; ++l, ++m)
NineSurface9_CopySurface(dst->surfaces[l],
src->surfaces[m], NULL, NULL);
if (src->dirty_rect.width == 0)
return D3D_OK;
pipe_box_to_rect(&rect, &src->dirty_rect);
for (l = 0; l < m; ++l)
rect_minify_inclusive(&rect);
for (l = 0; l <= last_level; ++l, ++m) {
fit_rect_format_inclusive(dst->base.base.info.format,
&rect,
dst->surfaces[l]->desc.Width,
dst->surfaces[l]->desc.Height);
NineSurface9_CopyMemToDefault(dst->surfaces[l],
src->surfaces[m],
(POINT *)&rect,
&rect);
rect_minify_inclusive(&rect);
}
u_box_origin_2d(0, 0, &src->dirty_rect);
} else
if (dstb->base.type == D3DRTYPE_CUBETEXTURE) {
struct NineCubeTexture9 *dst = NineCubeTexture9(dstb);
@ -1265,10 +1356,25 @@ NineDevice9_UpdateTexture( struct NineDevice9 *This,
/* GPUs usually have them stored as arrays of mip-mapped 2D textures. */
for (z = 0; z < 6; ++z) {
if (src->dirty_rect[z].width == 0)
continue;
pipe_box_to_rect(&rect, &src->dirty_rect[z]);
for (l = 0; l < m; ++l)
rect_minify_inclusive(&rect);
for (l = 0; l <= last_level; ++l, ++m) {
NineSurface9_CopySurface(dst->surfaces[l * 6 + z],
src->surfaces[m * 6 + z], NULL, NULL);
fit_rect_format_inclusive(dst->base.base.info.format,
&rect,
dst->surfaces[l * 6 + z]->desc.Width,
dst->surfaces[l * 6 + z]->desc.Height);
NineSurface9_CopyMemToDefault(dst->surfaces[l * 6 + z],
src->surfaces[m * 6 + z],
(POINT *)&rect,
&rect);
rect_minify_inclusive(&rect);
}
u_box_origin_2d(0, 0, &src->dirty_rect[z]);
m -= l;
}
} else
@ -1276,9 +1382,12 @@ NineDevice9_UpdateTexture( struct NineDevice9 *This,
struct NineVolumeTexture9 *dst = NineVolumeTexture9(dstb);
struct NineVolumeTexture9 *src = NineVolumeTexture9(srcb);
if (src->dirty_box.width == 0)
return D3D_OK;
for (l = 0; l <= last_level; ++l, ++m)
NineVolume9_CopyVolume(dst->volumes[l],
src->volumes[m], 0, 0, 0, NULL);
NineVolume9_CopyMemToDefault(dst->volumes[l],
src->volumes[m], 0, 0, 0, NULL);
u_box_3d(0, 0, 0, 0, 0, 0, &src->dirty_box);
} else{
assert(!"invalid texture type");
}
@ -1308,7 +1417,12 @@ NineDevice9_GetRenderTargetData( struct NineDevice9 *This,
user_assert(dst->desc.MultiSampleType < 2, D3DERR_INVALIDCALL);
user_assert(src->desc.MultiSampleType < 2, D3DERR_INVALIDCALL);
return NineSurface9_CopySurface(dst, src, NULL, NULL);
user_assert(src->desc.Width == dst->desc.Width, D3DERR_INVALIDCALL);
user_assert(src->desc.Height == dst->desc.Height, D3DERR_INVALIDCALL);
NineSurface9_CopyDefaultToMem(dst, src);
return D3D_OK;
}
HRESULT WINAPI
@ -1448,6 +1562,7 @@ NineDevice9_StretchRect( struct NineDevice9 *This,
blit.filter = Filter == D3DTEXF_LINEAR ?
PIPE_TEX_FILTER_LINEAR : PIPE_TEX_FILTER_NEAREST;
blit.scissor_enable = FALSE;
blit.alpha_blend = FALSE;
/* If both of a src and dst dimension are negative, flip them. */
if (blit.dst.box.width < 0 && blit.src.box.width < 0) {
@ -1464,8 +1579,12 @@ NineDevice9_StretchRect( struct NineDevice9 *This,
user_assert(!scaled || dst != src, D3DERR_INVALIDCALL);
user_assert(!scaled ||
!NineSurface9_IsOffscreenPlain(dst) ||
!NineSurface9_IsOffscreenPlain(dst), D3DERR_INVALIDCALL);
user_assert(!NineSurface9_IsOffscreenPlain(dst) ||
NineSurface9_IsOffscreenPlain(src), D3DERR_INVALIDCALL);
user_assert(NineSurface9_IsOffscreenPlain(dst) ||
dst->desc.Usage & (D3DUSAGE_RENDERTARGET | D3DUSAGE_DEPTHSTENCIL),
D3DERR_INVALIDCALL);
user_assert(!scaled ||
(!util_format_is_compressed(dst->base.info.format) &&
!util_format_is_compressed(src->base.info.format)),
@ -1561,11 +1680,8 @@ NineDevice9_ColorFill( struct NineDevice9 *This,
}
d3dcolor_to_pipe_color_union(&rgba, color);
fallback =
!This->screen->is_format_supported(This->screen, surf->base.info.format,
surf->base.info.target,
surf->base.info.nr_samples,
PIPE_BIND_RENDER_TARGET);
fallback = !(surf->base.info.bind & PIPE_BIND_RENDER_TARGET);
if (!fallback) {
psurf = NineSurface9_GetSurface(surf, 0);
if (!psurf)
@ -1774,7 +1890,7 @@ NineDevice9_Clear( struct NineDevice9 *This,
return D3D_OK;
d3dcolor_to_pipe_color_union(&rgba, Color);
nine_update_state(This, NINE_STATE_FB);
nine_update_state_framebuffer(This);
rect.x1 = This->state.viewport.X;
rect.y1 = This->state.viewport.Y;
@ -2012,8 +2128,10 @@ NineDevice9_SetLight( struct NineDevice9 *This,
return E_OUTOFMEMORY;
state->ff.num_lights = N;
for (; n < Index; ++n)
for (; n < Index; ++n) {
memset(&state->ff.light[n], 0, sizeof(D3DLIGHT9));
state->ff.light[n].Type = (D3DLIGHTTYPE)NINED3DLIGHT_INVALID;
}
}
state->ff.light[Index] = *pLight;
@ -2508,6 +2626,7 @@ NineDevice9_SetTextureStageState( struct NineDevice9 *This,
DWORD Value )
{
struct nine_state *state = This->update;
int bumpmap_index = -1;
DBG("Stage=%u Type=%u Value=%08x\n", Stage, Type, Value);
nine_dump_D3DTSS_value(DBG_FF, Type, Value);
@ -2516,6 +2635,36 @@ NineDevice9_SetTextureStageState( struct NineDevice9 *This,
user_assert(Type < Elements(state->ff.tex_stage[0]), D3DERR_INVALIDCALL);
state->ff.tex_stage[Stage][Type] = Value;
switch (Type) {
case D3DTSS_BUMPENVMAT00:
bumpmap_index = 4 * Stage;
break;
case D3DTSS_BUMPENVMAT10:
bumpmap_index = 4 * Stage + 1;
break;
case D3DTSS_BUMPENVMAT01:
bumpmap_index = 4 * Stage + 2;
break;
case D3DTSS_BUMPENVMAT11:
bumpmap_index = 4 * Stage + 3;
break;
case D3DTSS_BUMPENVLSCALE:
bumpmap_index = 4 * 8 + 2 * Stage;
break;
case D3DTSS_BUMPENVLOFFSET:
bumpmap_index = 4 * 8 + 2 * Stage + 1;
break;
case D3DTSS_TEXTURETRANSFORMFLAGS:
state->changed.group |= NINE_STATE_PS1X_SHADER;
break;
default:
break;
}
if (bumpmap_index >= 0) {
state->bumpmap_vars[bumpmap_index] = Value;
state->changed.group |= NINE_STATE_PS_CONST;
}
state->changed.group |= NINE_STATE_FF_PSSTAGES;
state->ff.changed.tex_stage[Stage][Type / 32] |= 1 << (Type % 32);
@ -2560,12 +2709,11 @@ NineDevice9_SetSamplerState( struct NineDevice9 *This,
if (Sampler >= D3DDMAPSAMPLER)
Sampler = Sampler - D3DDMAPSAMPLER + NINE_MAX_SAMPLERS_PS;
state->samp[Sampler][Type] = Value;
state->changed.group |= NINE_STATE_SAMPLER;
state->changed.sampler[Sampler] |= 1 << Type;
if (Type == D3DSAMP_SRGBTEXTURE)
state->changed.srgb = TRUE;
if (state->samp[Sampler][Type] != Value || unlikely(This->is_recording)) {
state->samp[Sampler][Type] = Value;
state->changed.group |= NINE_STATE_SAMPLER;
state->changed.sampler[Sampler] |= 1 << Type;
}
return D3D_OK;
}
@ -2724,7 +2872,7 @@ NineDevice9_DrawPrimitive( struct NineDevice9 *This,
DBG("iface %p, PrimitiveType %u, StartVertex %u, PrimitiveCount %u\n",
This, PrimitiveType, StartVertex, PrimitiveCount);
nine_update_state(This, ~0);
nine_update_state(This);
init_draw_info(&info, This, PrimitiveType, PrimitiveCount);
info.indexed = FALSE;
@ -2757,7 +2905,7 @@ NineDevice9_DrawIndexedPrimitive( struct NineDevice9 *This,
user_assert(This->state.idxbuf, D3DERR_INVALIDCALL);
user_assert(This->state.vdecl, D3DERR_INVALIDCALL);
nine_update_state(This, ~0);
nine_update_state(This);
init_draw_info(&info, This, PrimitiveType, PrimitiveCount);
info.indexed = TRUE;
@ -2789,7 +2937,7 @@ NineDevice9_DrawPrimitiveUP( struct NineDevice9 *This,
user_assert(pVertexStreamZeroData && VertexStreamZeroStride,
D3DERR_INVALIDCALL);
nine_update_state(This, ~0);
nine_update_state(This);
init_draw_info(&info, This, PrimitiveType, PrimitiveCount);
info.indexed = FALSE;
@ -2803,13 +2951,16 @@ NineDevice9_DrawPrimitiveUP( struct NineDevice9 *This,
vtxbuf.buffer = NULL;
vtxbuf.user_buffer = pVertexStreamZeroData;
if (!This->driver_caps.user_vbufs)
u_upload_data(This->upload,
if (!This->driver_caps.user_vbufs) {
u_upload_data(This->vertex_uploader,
0,
(info.max_index + 1) * VertexStreamZeroStride, /* XXX */
vtxbuf.user_buffer,
&vtxbuf.buffer_offset,
&vtxbuf.buffer);
u_upload_unmap(This->vertex_uploader);
vtxbuf.user_buffer = NULL;
}
This->pipe->set_vertex_buffers(This->pipe, 0, 1, &vtxbuf);
@ -2851,7 +3002,7 @@ NineDevice9_DrawIndexedPrimitiveUP( struct NineDevice9 *This,
user_assert(IndexDataFormat == D3DFMT_INDEX16 ||
IndexDataFormat == D3DFMT_INDEX32, D3DERR_INVALIDCALL);
nine_update_state(This, ~0);
nine_update_state(This);
init_draw_info(&info, This, PrimitiveType, PrimitiveCount);
info.indexed = TRUE;
@ -2872,23 +3023,28 @@ NineDevice9_DrawIndexedPrimitiveUP( struct NineDevice9 *This,
if (!This->driver_caps.user_vbufs) {
const unsigned base = info.min_index * VertexStreamZeroStride;
u_upload_data(This->upload,
u_upload_data(This->vertex_uploader,
base,
(info.max_index -
info.min_index + 1) * VertexStreamZeroStride, /* XXX */
(const uint8_t *)vbuf.user_buffer + base,
&vbuf.buffer_offset,
&vbuf.buffer);
u_upload_unmap(This->vertex_uploader);
/* Won't be used: */
vbuf.buffer_offset -= base;
vbuf.user_buffer = NULL;
}
if (!This->driver_caps.user_ibufs)
u_upload_data(This->upload,
if (!This->driver_caps.user_ibufs) {
u_upload_data(This->index_uploader,
0,
info.count * ibuf.index_size,
ibuf.user_buffer,
&ibuf.offset,
&ibuf.buffer);
u_upload_unmap(This->index_uploader);
ibuf.user_buffer = NULL;
}
This->pipe->set_vertex_buffers(This->pipe, 0, 1, &vbuf);
This->pipe->set_index_buffer(This->pipe, &ibuf);
@ -2935,7 +3091,7 @@ NineDevice9_ProcessVertices( struct NineDevice9 *This,
if (!screen->get_param(screen, PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS))
STUB(D3DERR_INVALIDCALL);
nine_update_state(This, ~0);
nine_update_state(This);
/* TODO: Create shader with stream output. */
STUB(D3DERR_INVALIDCALL);
@ -3105,6 +3261,13 @@ NineDevice9_SetVertexShader( struct NineDevice9 *This,
DBG("This=%p pShader=%p\n", This, pShader);
if (!This->is_recording && state->vs == (struct NineVertexShader9*)pShader)
return D3D_OK;
/* ff -> non-ff: commit back non-ff constants */
if (!state->vs && pShader)
state->commit |= NINE_STATE_COMMIT_CONST_VS;
nine_bind(&state->vs, pShader);
state->changed.group |= NINE_STATE_VS;
@ -3139,6 +3302,12 @@ NineDevice9_SetVertexShaderConstantF( struct NineDevice9 *This,
return D3D_OK;
user_assert(pConstantData, D3DERR_INVALIDCALL);
if (!This->is_recording) {
if (!memcmp(&state->vs_const_f[StartRegister * 4], pConstantData,
Vector4fCount * 4 * sizeof(state->vs_const_f[0])))
return D3D_OK;
}
memcpy(&state->vs_const_f[StartRegister * 4],
pConstantData,
Vector4fCount * 4 * sizeof(state->vs_const_f[0]));
@ -3188,6 +3357,11 @@ NineDevice9_SetVertexShaderConstantI( struct NineDevice9 *This,
user_assert(pConstantData, D3DERR_INVALIDCALL);
if (This->driver_caps.vs_integer) {
if (!This->is_recording) {
if (!memcmp(&state->vs_const_i[StartRegister][0], pConstantData,
Vector4iCount * sizeof(state->vs_const_i[0])))
return D3D_OK;
}
memcpy(&state->vs_const_i[StartRegister][0],
pConstantData,
Vector4iCount * sizeof(state->vs_const_i[0]));
@ -3252,6 +3426,16 @@ NineDevice9_SetVertexShaderConstantB( struct NineDevice9 *This,
user_assert(StartRegister + BoolCount <= NINE_MAX_CONST_B, D3DERR_INVALIDCALL);
user_assert(pConstantData, D3DERR_INVALIDCALL);
if (!This->is_recording) {
bool noChange = true;
for (i = 0; i < BoolCount; i++) {
if (!!state->vs_const_b[StartRegister + i] != !!pConstantData[i])
noChange = false;
}
if (noChange)
return D3D_OK;
}
for (i = 0; i < BoolCount; i++)
state->vs_const_b[StartRegister + i] = pConstantData[i] ? bool_true : 0;
@ -3433,6 +3617,13 @@ NineDevice9_SetPixelShader( struct NineDevice9 *This,
DBG("This=%p pShader=%p\n", This, pShader);
if (!This->is_recording && state->ps == (struct NinePixelShader9*)pShader)
return D3D_OK;
/* ff -> non-ff: commit back non-ff constants */
if (!state->ps && pShader)
state->commit |= NINE_STATE_COMMIT_CONST_PS;
nine_bind(&state->ps, pShader);
state->changed.group |= NINE_STATE_PS;
@ -3473,6 +3664,12 @@ NineDevice9_SetPixelShaderConstantF( struct NineDevice9 *This,
return D3D_OK;
user_assert(pConstantData, D3DERR_INVALIDCALL);
if (!This->is_recording) {
if (!memcmp(&state->ps_const_f[StartRegister * 4], pConstantData,
Vector4fCount * 4 * sizeof(state->ps_const_f[0])))
return D3D_OK;
}
memcpy(&state->ps_const_f[StartRegister * 4],
pConstantData,
Vector4fCount * 4 * sizeof(state->ps_const_f[0]));
@ -3522,6 +3719,11 @@ NineDevice9_SetPixelShaderConstantI( struct NineDevice9 *This,
user_assert(pConstantData, D3DERR_INVALIDCALL);
if (This->driver_caps.ps_integer) {
if (!This->is_recording) {
if (!memcmp(&state->ps_const_i[StartRegister][0], pConstantData,
Vector4iCount * sizeof(state->ps_const_i[0])))
return D3D_OK;
}
memcpy(&state->ps_const_i[StartRegister][0],
pConstantData,
Vector4iCount * sizeof(state->ps_const_i[0]));
@ -3585,6 +3787,16 @@ NineDevice9_SetPixelShaderConstantB( struct NineDevice9 *This,
user_assert(StartRegister + BoolCount <= NINE_MAX_CONST_B, D3DERR_INVALIDCALL);
user_assert(pConstantData, D3DERR_INVALIDCALL);
if (!This->is_recording) {
bool noChange = true;
for (i = 0; i < BoolCount; i++) {
if (!!state->ps_const_b[StartRegister + i] != !!pConstantData[i])
noChange = false;
}
if (noChange)
return D3D_OK;
}
for (i = 0; i < BoolCount; i++)
state->ps_const_b[StartRegister + i] = pConstantData[i] ? bool_true : 0;

13
src/gallium/state_trackers/nine/device9.h
View file

@ -69,6 +69,7 @@ struct NineDevice9
struct nine_state state; /* device state */
struct list_head update_textures;
struct list_head managed_textures;
boolean is_recording;
boolean in_scene;
@ -83,7 +84,8 @@ struct NineDevice9
uint16_t max_ps_const_f;
struct pipe_resource *dummy_texture;
struct pipe_sampler_view *dummy_sampler;
struct pipe_sampler_view *dummy_sampler_view;
struct pipe_sampler_state dummy_sampler_state;
struct gen_mipmap_state *gen_mipmap;
@ -113,6 +115,7 @@ struct NineDevice9
struct {
boolean user_vbufs;
boolean user_ibufs;
boolean user_cbufs;
boolean window_space_position_support;
boolean vs_integer;
boolean ps_integer;
@ -122,7 +125,9 @@ struct NineDevice9
boolean buggy_barycentrics;
} driver_bugs;
struct u_upload_mgr *upload;
struct u_upload_mgr *vertex_uploader;
struct u_upload_mgr *index_uploader;
struct u_upload_mgr *constbuf_uploader;
struct nine_range_pool range_pool;
@ -180,10 +185,6 @@ NineDevice9_GetCSO( struct NineDevice9 *This );
const D3DCAPS9 *
NineDevice9_GetCaps( struct NineDevice9 *This );
/* Mask: 0x1 = constant buffers, 0x2 = stipple */
void
NineDevice9_RestoreNonCSOState( struct NineDevice9 *This, unsigned mask );
/*** Direct3D public ***/
HRESULT WINAPI

377
src/gallium/state_trackers/nine/nine_ff.c
View file

@ -22,6 +22,7 @@
#include "tgsi/tgsi_dump.h"
#include "util/u_box.h"
#include "util/u_hash_table.h"
#include "util/u_upload_mgr.h"
#define NINE_TGSI_LAZY_DEVS 1
@ -30,13 +31,6 @@
#define NINE_FF_NUM_VS_CONST 256
#define NINE_FF_NUM_PS_CONST 24
#define NINED3DTSS_TCI_DISABLE 0
#define NINED3DTSS_TCI_PASSTHRU 1
#define NINED3DTSS_TCI_CAMERASPACENORMAL 2
#define NINED3DTSS_TCI_CAMERASPACEPOSITION 3
#define NINED3DTSS_TCI_CAMERASPACEREFLECTIONVECTOR 4
#define NINED3DTSS_TCI_SPHEREMAP 5
struct fvec4
{
float x, y, z, w;
@ -63,16 +57,20 @@ struct nine_ff_vs_key
uint32_t fog_range : 1;
uint32_t color0in_one : 1;
uint32_t color1in_one : 1;
uint32_t pad1 : 8;
uint32_t tc_gen : 24; /* 8 * 3 bits */
uint32_t pad2 : 8;
uint32_t tc_idx : 24;
uint32_t fog : 1;
uint32_t pad1 : 7;
uint32_t tc_dim_input: 16; /* 8 * 2 bits */
uint32_t pad2 : 16;
uint32_t tc_dim_output: 24; /* 8 * 3 bits */
uint32_t pad3 : 8;
uint32_t tc_dim : 24; /* 8 * 3 bits */
uint32_t tc_gen : 24; /* 8 * 3 bits */
uint32_t pad4 : 8;
uint32_t tc_idx : 24;
uint32_t pad5 : 8;
uint32_t passthrough;
};
uint64_t value64[2]; /* don't forget to resize VertexShader9.ff_key */
uint32_t value32[4];
uint64_t value64[3]; /* don't forget to resize VertexShader9.ff_key */
uint32_t value32[6];
};
};
@ -106,15 +104,18 @@ struct nine_ff_ps_key
uint32_t alphaarg2 : 3;
uint32_t resultarg : 1; /* CURRENT:0 or TEMP:1 */
uint32_t textarget : 2; /* 1D/2D/3D/CUBE */
uint32_t projected : 1;
uint32_t pad : 1;
/* that's 32 bit exactly */
} ts[8];
uint32_t fog : 1; /* for vFog with programmable VS */
uint32_t projected : 16;
uint32_t fog : 1; /* for vFog coming from VS */
uint32_t fog_mode : 2;
uint32_t specular : 1; /* 9 32-bit words with this */
uint32_t specular : 1;
uint32_t pad1 : 12; /* 9 32-bit words with this */
uint8_t colorarg_b4[3];
uint8_t colorarg_b5[3];
uint8_t alphaarg_b4[3]; /* 11 32-bit words plus a byte */
uint8_t pad2[3];
};
uint64_t value64[6]; /* don't forget to resize PixelShader9.ff_key */
uint32_t value32[12];
@ -222,7 +223,6 @@ static void nine_ureg_tgsi_dump(struct ureg_program *ureg, boolean override)
* CONST[28].x___ RS.FogEnd
* CONST[28]._y__ 1.0f / (RS.FogEnd - RS.FogStart)
* CONST[28].__z_ RS.FogDensity
* CONST[29] RS.FogColor
* CONST[30].x___ TWEENFACTOR
*
@ -334,16 +334,15 @@ nine_ff_build_vs(struct NineDevice9 *device, struct vs_build_ctx *vs)
{
const struct nine_ff_vs_key *key = vs->key;
struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_VERTEX);
struct ureg_dst oPos, oCol[2], oTex[8], oPsz, oFog;
struct ureg_dst rCol[2]; /* oCol if no fog, TEMP otherwise */
struct ureg_dst oPos, oCol[2], oPsz, oFog;
struct ureg_dst rVtx, rNrm;
struct ureg_dst r[8];
struct ureg_dst AR;
struct ureg_dst tmp, tmp_x, tmp_z;
struct ureg_dst tmp, tmp_x, tmp_y, tmp_z;
unsigned i, c;
unsigned label[32], l = 0;
unsigned num_r = 8;
boolean need_rNrm = key->lighting || key->pointscale;
boolean need_rNrm = key->lighting || key->pointscale || key->passthrough & (1 << NINE_DECLUSAGE_NORMAL);
boolean need_rVtx = key->lighting || key->fog_mode;
const unsigned texcoord_sn = get_texcoord_sn(device->screen);
@ -406,9 +405,9 @@ nine_ff_build_vs(struct NineDevice9 *device, struct vs_build_ctx *vs)
if (key->vertexpointsize)
vs->aPsz = build_vs_add_input(vs, NINE_DECLUSAGE_PSIZE);
if (key->vertexblend_indexed)
if (key->vertexblend_indexed || key->passthrough & (1 << NINE_DECLUSAGE_BLENDINDICES))
vs->aInd = build_vs_add_input(vs, NINE_DECLUSAGE_BLENDINDICES);
if (key->vertexblend)
if (key->vertexblend || key->passthrough & (1 << NINE_DECLUSAGE_BLENDWEIGHT))
vs->aWgt = build_vs_add_input(vs, NINE_DECLUSAGE_BLENDWEIGHT);
if (key->vertextween) {
vs->aVtx1 = build_vs_add_input(vs, NINE_DECLUSAGE_i(POSITION,1));
@ -420,19 +419,16 @@ nine_ff_build_vs(struct NineDevice9 *device, struct vs_build_ctx *vs)
oPos = ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0); /* HPOS */
oCol[0] = ureg_saturate(ureg_DECL_output(ureg, TGSI_SEMANTIC_COLOR, 0));
oCol[1] = ureg_saturate(ureg_DECL_output(ureg, TGSI_SEMANTIC_COLOR, 1));
if (key->fog || key->passthrough & (1 << NINE_DECLUSAGE_FOG)) {
oFog = ureg_DECL_output(ureg, TGSI_SEMANTIC_FOG, 0);
oFog = ureg_writemask(oFog, TGSI_WRITEMASK_X);
}
if (key->vertexpointsize || key->pointscale) {
oPsz = ureg_DECL_output_masked(ureg, TGSI_SEMANTIC_PSIZE, 0,
TGSI_WRITEMASK_X, 0, 1);
oPsz = ureg_writemask(oPsz, TGSI_WRITEMASK_X);
}
if (key->fog_mode) {
/* We apply fog to the vertex colors, oFog is for programmable shaders only ?
*/
oFog = ureg_DECL_output_masked(ureg, TGSI_SEMANTIC_FOG, 0,
TGSI_WRITEMASK_X, 0, 1);
oFog = ureg_writemask(oFog, TGSI_WRITEMASK_X);
}
/* Declare TEMPs:
*/
@ -440,18 +436,11 @@ nine_ff_build_vs(struct NineDevice9 *device, struct vs_build_ctx *vs)
r[i] = ureg_DECL_local_temporary(ureg);
tmp = r[0];
tmp_x = ureg_writemask(tmp, TGSI_WRITEMASK_X);
tmp_y = ureg_writemask(tmp, TGSI_WRITEMASK_Y);
tmp_z = ureg_writemask(tmp, TGSI_WRITEMASK_Z);
if (key->lighting || key->vertexblend)
AR = ureg_DECL_address(ureg);
if (key->fog_mode) {
rCol[0] = r[2];
rCol[1] = r[3];
} else {
rCol[0] = oCol[0];
rCol[1] = oCol[1];
}
rVtx = ureg_writemask(r[1], TGSI_WRITEMASK_XYZ);
rNrm = ureg_writemask(r[2], TGSI_WRITEMASK_XYZ);
@ -560,8 +549,6 @@ nine_ff_build_vs(struct NineDevice9 *device, struct vs_build_ctx *vs)
ureg_CLAMP(ureg, oPsz, vs->aPsz, _XXXX(cPsz1), _YYYY(cPsz1));
#endif
} else if (key->pointscale) {
struct ureg_dst tmp_x = ureg_writemask(tmp, TGSI_WRITEMASK_X);
struct ureg_dst tmp_y = ureg_writemask(tmp, TGSI_WRITEMASK_Y);
struct ureg_src cPsz1 = ureg_DECL_constant(ureg, 26);
struct ureg_src cPsz2 = ureg_DECL_constant(ureg, 27);
@ -582,72 +569,85 @@ nine_ff_build_vs(struct NineDevice9 *device, struct vs_build_ctx *vs)
#endif
}
/* Texture coordinate generation:
* XXX: D3DTTFF_PROJECTED, transform matrix
*/
for (i = 0; i < 8; ++i) {
struct ureg_dst dst[5];
struct ureg_src src;
unsigned c;
struct ureg_dst oTex, input_coord, transformed, t;
unsigned c, writemask;
const unsigned tci = (key->tc_gen >> (i * 3)) & 0x7;
const unsigned idx = (key->tc_idx >> (i * 3)) & 0x7;
const unsigned dim = (key->tc_dim >> (i * 3)) & 0x7;
unsigned dim_input = 1 + ((key->tc_dim_input >> (i * 2)) & 0x3);
const unsigned dim_output = (key->tc_dim_output >> (i * 3)) & 0x7;
/* No texture output of index s */
if (tci == NINED3DTSS_TCI_DISABLE)
continue;
oTex[i] = ureg_DECL_output(ureg, texcoord_sn, i);
if (tci == NINED3DTSS_TCI_PASSTHRU)
vs->aTex[idx] = build_vs_add_input(vs, NINE_DECLUSAGE_i(TEXCOORD,idx));
if (!dim) {
dst[c = 4] = oTex[i];
} else {
dst[4] = r[5];
src = ureg_src(dst[4]);
for (c = 0; c < (dim - 1); ++c)
dst[c] = ureg_writemask(tmp, (1 << dim) - 1);
dst[c] = ureg_writemask(oTex[i], (1 << dim) - 1);
}
oTex = ureg_DECL_output(ureg, texcoord_sn, i);
input_coord = r[5];
transformed = r[6];
/* Get the coordinate */
switch (tci) {
case NINED3DTSS_TCI_PASSTHRU:
ureg_MOV(ureg, dst[4], vs->aTex[idx]);
/* NINED3DTSS_TCI_PASSTHRU => Use texcoord coming from index idx *
* Else the idx is used only to determine wrapping mode. */
vs->aTex[idx] = build_vs_add_input(vs, NINE_DECLUSAGE_i(TEXCOORD,idx));
ureg_MOV(ureg, input_coord, vs->aTex[idx]);
break;
case NINED3DTSS_TCI_CAMERASPACENORMAL:
assert(dim <= 3);
ureg_MOV(ureg, ureg_writemask(dst[4], TGSI_WRITEMASK_XYZ), ureg_src(rNrm));
ureg_MOV(ureg, ureg_writemask(dst[4], TGSI_WRITEMASK_W), ureg_imm1f(ureg, 1.0f));
ureg_MOV(ureg, ureg_writemask(input_coord, TGSI_WRITEMASK_XYZ), ureg_src(rNrm));
ureg_MOV(ureg, ureg_writemask(input_coord, TGSI_WRITEMASK_W), ureg_imm1f(ureg, 1.0f));
dim_input = 4;
break;
case NINED3DTSS_TCI_CAMERASPACEPOSITION:
ureg_MOV(ureg, ureg_writemask(dst[4], TGSI_WRITEMASK_XYZ), ureg_src(rVtx));
ureg_MOV(ureg, ureg_writemask(dst[4], TGSI_WRITEMASK_W), ureg_imm1f(ureg, 1.0f));
ureg_MOV(ureg, ureg_writemask(input_coord, TGSI_WRITEMASK_XYZ), ureg_src(rVtx));
ureg_MOV(ureg, ureg_writemask(input_coord, TGSI_WRITEMASK_W), ureg_imm1f(ureg, 1.0f));
dim_input = 4;
break;
case NINED3DTSS_TCI_CAMERASPACEREFLECTIONVECTOR:
tmp.WriteMask = TGSI_WRITEMASK_XYZ;
ureg_DP3(ureg, tmp_x, ureg_src(rVtx), ureg_src(rNrm));
ureg_MUL(ureg, tmp, ureg_src(rNrm), _X(tmp));
ureg_ADD(ureg, tmp, ureg_src(tmp), ureg_src(tmp));
ureg_SUB(ureg, ureg_writemask(dst[4], TGSI_WRITEMASK_XYZ), ureg_src(rVtx), ureg_src(tmp));
ureg_MOV(ureg, ureg_writemask(dst[4], TGSI_WRITEMASK_W), ureg_imm1f(ureg, 1.0f));
ureg_SUB(ureg, ureg_writemask(input_coord, TGSI_WRITEMASK_XYZ), ureg_src(rVtx), ureg_src(tmp));
ureg_MOV(ureg, ureg_writemask(input_coord, TGSI_WRITEMASK_W), ureg_imm1f(ureg, 1.0f));
dim_input = 4;
tmp.WriteMask = TGSI_WRITEMASK_XYZW;
break;
case NINED3DTSS_TCI_SPHEREMAP:
assert(!"TODO");
break;
default:
assert(0);
break;
}
if (!dim)
continue;
dst[c].WriteMask = ~dst[c].WriteMask;
if (dst[c].WriteMask)
ureg_MOV(ureg, dst[c], src); /* store untransformed components */
dst[c].WriteMask = ~dst[c].WriteMask;
if (dim > 0) ureg_MUL(ureg, dst[0], _XXXX(src), _CONST(128 + i * 4));
if (dim > 1) ureg_MAD(ureg, dst[1], _YYYY(src), _CONST(129 + i * 4), ureg_src(tmp));
if (dim > 2) ureg_MAD(ureg, dst[2], _ZZZZ(src), _CONST(130 + i * 4), ureg_src(tmp));
if (dim > 3) ureg_MAD(ureg, dst[3], _WWWW(src), _CONST(131 + i * 4), ureg_src(tmp));
/* Apply the transformation */
/* dim_output == 0 => do not transform the components.
* XYZRHW also disables transformation */
if (!dim_output || key->position_t) {
transformed = input_coord;
writemask = TGSI_WRITEMASK_XYZW;
} else {
for (c = 0; c < dim_output; c++) {
t = ureg_writemask(transformed, 1 << c);
switch (dim_input) {
/* dim_input = 1 2 3: -> we add trailing 1 to input*/
case 1: ureg_MAD(ureg, t, _X(input_coord), _XXXX(_CONST(128 + i * 4 + c)), _YYYY(_CONST(128 + i * 4 + c)));
break;
case 2: ureg_DP2(ureg, t, ureg_src(input_coord), _CONST(128 + i * 4 + c));
ureg_ADD(ureg, t, ureg_src(transformed), _ZZZZ(_CONST(128 + i * 4 + c)));
break;
case 3: ureg_DP3(ureg, t, ureg_src(input_coord), _CONST(128 + i * 4 + c));
ureg_ADD(ureg, t, ureg_src(transformed), _WWWW(_CONST(128 + i * 4 + c)));
break;
case 4: ureg_DP4(ureg, t, ureg_src(input_coord), _CONST(128 + i * 4 + c)); break;
default:
assert(0);
}
}
writemask = (1 << dim_output) - 1;
}
ureg_MOV(ureg, ureg_writemask(oTex, writemask), ureg_src(transformed));
}
/* === Lighting:
@ -692,8 +692,6 @@ nine_ff_build_vs(struct NineDevice9 *device, struct vs_build_ctx *vs)
* specular += light.specular * atten * powFact;
*/
if (key->lighting) {
struct ureg_dst tmp_y = ureg_writemask(tmp, TGSI_WRITEMASK_Y);
struct ureg_dst rAtt = ureg_writemask(r[1], TGSI_WRITEMASK_W);
struct ureg_dst rHit = ureg_writemask(r[3], TGSI_WRITEMASK_XYZ);
struct ureg_dst rMid = ureg_writemask(r[4], TGSI_WRITEMASK_XYZ);
@ -851,22 +849,22 @@ nine_ff_build_vs(struct NineDevice9 *device, struct vs_build_ctx *vs)
ureg_MAD(ureg, ureg_writemask(tmp, TGSI_WRITEMASK_XYZ), vs->mtlA, ureg_src(tmp), vs->mtlE);
ureg_ADD(ureg, ureg_writemask(tmp, TGSI_WRITEMASK_W ), vs->mtlA, vs->mtlE);
}
ureg_MAD(ureg, rCol[0], ureg_src(rD), vs->mtlD, ureg_src(tmp));
ureg_MUL(ureg, rCol[1], ureg_src(rS), vs->mtlS);
ureg_MAD(ureg, oCol[0], ureg_src(rD), vs->mtlD, ureg_src(tmp));
ureg_MUL(ureg, oCol[1], ureg_src(rS), vs->mtlS);
} else
/* COLOR */
if (key->darkness) {
if (key->mtl_emissive == 0 && key->mtl_ambient == 0) {
ureg_MAD(ureg, rCol[0], vs->mtlD, ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f), _CONST(19));
ureg_MAD(ureg, oCol[0], vs->mtlD, ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f), _CONST(19));
} else {
ureg_MAD(ureg, ureg_writemask(rCol[0], TGSI_WRITEMASK_XYZ), vs->mtlA, _CONST(25), vs->mtlE);
ureg_MAD(ureg, ureg_writemask(oCol[0], TGSI_WRITEMASK_XYZ), vs->mtlA, _CONST(25), vs->mtlE);
ureg_ADD(ureg, ureg_writemask(tmp, TGSI_WRITEMASK_W), vs->mtlA, vs->mtlE);
ureg_ADD(ureg, ureg_writemask(rCol[0], TGSI_WRITEMASK_W), vs->mtlD, _W(tmp));
ureg_ADD(ureg, ureg_writemask(oCol[0], TGSI_WRITEMASK_W), vs->mtlD, _W(tmp));
}
ureg_MUL(ureg, rCol[1], ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f), vs->mtlS);
ureg_MUL(ureg, oCol[1], ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f), vs->mtlS);
} else {
ureg_MOV(ureg, rCol[0], vs->aCol[0]);
ureg_MOV(ureg, rCol[1], vs->aCol[1]);
ureg_MOV(ureg, oCol[0], vs->aCol[0]);
ureg_MOV(ureg, oCol[1], vs->aCol[1]);
}
/* === Process fog.
@ -874,10 +872,6 @@ nine_ff_build_vs(struct NineDevice9 *device, struct vs_build_ctx *vs)
* exp(x) = ex2(log2(e) * x)
*/
if (key->fog_mode) {
/* Fog doesn't affect alpha, TODO: combine with light code output */
ureg_MOV(ureg, ureg_writemask(oCol[0], TGSI_WRITEMASK_W), _W(rCol[0]));
ureg_MOV(ureg, ureg_writemask(oCol[1], TGSI_WRITEMASK_W), _W(rCol[1]));
if (key->position_t) {
ureg_MOV(ureg, ureg_saturate(tmp_x), ureg_scalar(vs->aCol[1], TGSI_SWIZZLE_W));
} else
@ -905,10 +899,58 @@ nine_ff_build_vs(struct NineDevice9 *device, struct vs_build_ctx *vs)
ureg_MUL(ureg, ureg_saturate(tmp_x), _X(tmp), _YYYY(_CONST(28)));
}
ureg_MOV(ureg, oFog, _X(tmp));
ureg_LRP(ureg, ureg_writemask(oCol[0], TGSI_WRITEMASK_XYZ), _X(tmp), ureg_src(rCol[0]), _CONST(29));
ureg_LRP(ureg, ureg_writemask(oCol[1], TGSI_WRITEMASK_XYZ), _X(tmp), ureg_src(rCol[1]), _CONST(29));
} else if (key->fog && !(key->passthrough & (1 << NINE_DECLUSAGE_FOG))) {
ureg_MOV(ureg, oFog, ureg_scalar(vs->aCol[1], TGSI_SWIZZLE_W));
}
if (key->passthrough & (1 << NINE_DECLUSAGE_BLENDWEIGHT)) {
struct ureg_src input;
struct ureg_dst output;
input = vs->aWgt;
output = ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 18);
ureg_MOV(ureg, output, input);
}
if (key->passthrough & (1 << NINE_DECLUSAGE_BLENDINDICES)) {
struct ureg_src input;
struct ureg_dst output;
input = vs->aInd;
output = ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 19);
ureg_MOV(ureg, output, input);
}
if (key->passthrough & (1 << NINE_DECLUSAGE_NORMAL)) {
struct ureg_src input;
struct ureg_dst output;
input = vs->aNrm;
output = ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 20);
ureg_MOV(ureg, output, input);
}
if (key->passthrough & (1 << NINE_DECLUSAGE_TANGENT)) {
struct ureg_src input;
struct ureg_dst output;
input = build_vs_add_input(vs, NINE_DECLUSAGE_TANGENT);
output = ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 21);
ureg_MOV(ureg, output, input);
}
if (key->passthrough & (1 << NINE_DECLUSAGE_BINORMAL)) {
struct ureg_src input;
struct ureg_dst output;
input = build_vs_add_input(vs, NINE_DECLUSAGE_BINORMAL);
output = ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 22);
ureg_MOV(ureg, output, input);
}
if (key->passthrough & (1 << NINE_DECLUSAGE_FOG)) {
struct ureg_src input;
struct ureg_dst output;
input = build_vs_add_input(vs, NINE_DECLUSAGE_FOG);
input = ureg_scalar(input, TGSI_SWIZZLE_X);
output = oFog;
ureg_MOV(ureg, output, input);
}
if (key->passthrough & (1 << NINE_DECLUSAGE_DEPTH)) {
(void) 0; /* TODO: replace z of position output ? */
}
if (key->position_t && device->driver_caps.window_space_position_support)
ureg_property(ureg, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, TRUE);
@ -1270,10 +1312,18 @@ nine_ff_build_ps(struct NineDevice9 *device, struct nine_ff_ps_key *key)
if (key->ts[s].colorop == D3DTOP_BUMPENVMAP ||
key->ts[s].colorop == D3DTOP_BUMPENVMAPLUMINANCE) {
}
if (key->ts[s].projected)
ureg_TXP(ureg, ps.rTex, target, ps.vT[s], ps.s[s]);
else
if (key->projected & (3 << (s *2))) {
unsigned dim = 1 + ((key->projected >> (2 * s)) & 3);
if (dim == 4)
ureg_TXP(ureg, ps.rTex, target, ps.vT[s], ps.s[s]);
else {
ureg_RCP(ureg, ureg_writemask(ps.rTmp, TGSI_WRITEMASK_X), ureg_scalar(ps.vT[s], dim-1));
ureg_MUL(ureg, ps.rTmp, _XXXX(ps.rTmpSrc), ps.vT[s]);
ureg_TEX(ureg, ps.rTex, target, ps.rTmpSrc, ps.s[s]);
}
} else {
ureg_TEX(ureg, ps.rTex, target, ps.vT[s], ps.s[s]);
}
}
if (s == 0 &&
@ -1316,6 +1366,10 @@ nine_ff_build_ps(struct NineDevice9 *device, struct nine_ff_ps_key *key)
colorarg[2] != alphaarg[2])
dst.WriteMask = TGSI_WRITEMASK_XYZ;
/* Special DOTPRODUCT behaviour (see wine tests) */
if (key->ts[s].colorop == D3DTOP_DOTPRODUCT3)
dst.WriteMask = TGSI_WRITEMASK_XYZW;
if (used_c & 0x1) arg[0] = ps_get_ts_arg(&ps, colorarg[0]);
if (used_c & 0x2) arg[1] = ps_get_ts_arg(&ps, colorarg[1]);
if (used_c & 0x4) arg[2] = ps_get_ts_arg(&ps, colorarg[2]);
@ -1406,12 +1460,18 @@ nine_ff_get_vs(struct NineDevice9 *device)
else if (usage % NINE_DECLUSAGE_COUNT == NINE_DECLUSAGE_TEXCOORD) {
s = usage / NINE_DECLUSAGE_COUNT;
if (s < 8)
input_texture_coord[s] = 1;
input_texture_coord[s] = nine_decltype_get_dim(state->vdecl->decls[i].Type);
else
DBG("FF given texture coordinate >= 8. Ignoring\n");
}
} else if (usage < NINE_DECLUSAGE_NONE)
key.passthrough |= 1 << usage;
}
}
/* ff vs + ps 3.0: some elements are passed to the ps (wine test).
* We do restrict to indices 0 */
key.passthrough &= ~((1 << NINE_DECLUSAGE_POSITION) | (1 << NINE_DECLUSAGE_PSIZE) |
(1 << NINE_DECLUSAGE_TEXCOORD) | (1 << NINE_DECLUSAGE_POSITIONT) |
(1 << NINE_DECLUSAGE_TESSFACTOR) | (1 << NINE_DECLUSAGE_SAMPLE));
if (!key.vertexpointsize)
key.pointscale = !!state->rs[D3DRS_POINTSCALEENABLE];
@ -1427,6 +1487,7 @@ nine_ff_get_vs(struct NineDevice9 *device)
key.mtl_specular = state->rs[D3DRS_SPECULARMATERIALSOURCE];
key.mtl_emissive = state->rs[D3DRS_EMISSIVEMATERIALSOURCE];
}
key.fog = !!state->rs[D3DRS_FOGENABLE];
key.fog_mode = state->rs[D3DRS_FOGENABLE] ? state->rs[D3DRS_FOGVERTEXMODE] : 0;
if (key.fog_mode)
key.fog_range = !key.position_t && state->rs[D3DRS_RANGEFOGENABLE];
@ -1448,7 +1509,7 @@ nine_ff_get_vs(struct NineDevice9 *device)
for (s = 0; s < 8; ++s) {
unsigned gen = (state->ff.tex_stage[s][D3DTSS_TEXCOORDINDEX] >> 16) + 1;
unsigned dim = MIN2(state->ff.tex_stage[s][D3DTSS_TEXTURETRANSFORMFLAGS] & 0x7, 4);
unsigned dim;
if (key.position_t && gen > NINED3DTSS_TCI_PASSTHRU)
gen = NINED3DTSS_TCI_PASSTHRU;
@ -1458,7 +1519,14 @@ nine_ff_get_vs(struct NineDevice9 *device)
key.tc_gen |= gen << (s * 3);
key.tc_idx |= (state->ff.tex_stage[s][D3DTSS_TEXCOORDINDEX] & 7) << (s * 3);
key.tc_dim |= dim << (s * 3);
key.tc_dim_input |= ((input_texture_coord[s]-1) & 0x3) << (s * 2);
dim = state->ff.tex_stage[s][D3DTSS_TEXTURETRANSFORMFLAGS] & 0x7;
if (dim > 4)
dim = input_texture_coord[s];
if (dim == 1) /* NV behaviour */
dim = 0;
key.tc_dim_output |= dim << (s * 3);
}
vs = util_hash_table_get(device->ff.ht_vs, &key);
@ -1473,6 +1541,7 @@ nine_ff_get_vs(struct NineDevice9 *device)
memcpy(&vs->ff_key, &key, sizeof(vs->ff_key));
err = util_hash_table_set(device->ff.ht_vs, &vs->ff_key, vs);
(void)err;
assert(err == PIPE_OK);
device->ff.num_vs++;
NineUnknown_ConvertRefToBind(NineUnknown(vs));
@ -1543,8 +1612,6 @@ nine_ff_get_ps(struct NineDevice9 *device)
}
key.ts[s].resultarg = state->ff.tex_stage[s][D3DTSS_RESULTARG] == D3DTA_TEMP;
key.ts[s].projected = !!(state->ff.tex_stage[s][D3DTSS_TEXTURETRANSFORMFLAGS] & D3DTTFF_PROJECTED);
if (state->texture[s]) {
switch (state->texture[s]->base.type) {
case D3DRTYPE_TEXTURE: key.ts[s].textarget = 1; break;
@ -1558,10 +1625,14 @@ nine_ff_get_ps(struct NineDevice9 *device)
key.ts[s].textarget = 1;
}
}
key.projected = nine_ff_get_projected_key(state);
for (; s < 8; ++s)
key.ts[s].colorop = key.ts[s].alphaop = D3DTOP_DISABLE;
if (state->rs[D3DRS_FOGENABLE])
key.fog_mode = state->rs[D3DRS_FOGTABLEMODE];
key.fog = !!state->rs[D3DRS_FOGENABLE];
ps = util_hash_table_get(device->ff.ht_ps, &key);
if (ps)
@ -1573,6 +1644,7 @@ nine_ff_get_ps(struct NineDevice9 *device)
memcpy(&ps->ff_key, &key, sizeof(ps->ff_key));
err = util_hash_table_set(device->ff.ht_ps, &ps->ff_key, ps);
(void)err;
assert(err == PIPE_OK);
device->ff.num_ps++;
NineUnknown_ConvertRefToBind(NineUnknown(ps));
@ -1689,7 +1761,6 @@ nine_ff_load_point_and_fog_params(struct NineDevice9 *device)
if (isinf(dst[28].y))
dst[28].y = 0.0f;
dst[28].z = asfloat(state->rs[D3DRS_FOGDENSITY]);
d3dcolor_to_rgba(&dst[29].x, state->rs[D3DRS_FOGCOLOR]);
}
static void
@ -1703,7 +1774,7 @@ nine_ff_load_tex_matrices(struct NineDevice9 *device)
return;
for (s = 0; s < 8; ++s) {
if (IS_D3DTS_DIRTY(state, TEXTURE0 + s))
M[32 + s] = *nine_state_access_transform(state, D3DTS_TEXTURE0 + s, FALSE);
nine_d3d_matrix_transpose(&M[32 + s], nine_state_access_transform(state, D3DTS_TEXTURE0 + s, FALSE));
}
}
@ -1762,28 +1833,22 @@ nine_ff_load_viewport_info(struct NineDevice9 *device)
void
nine_ff_update(struct NineDevice9 *device)
{
struct pipe_context *pipe = device->pipe;
struct nine_state *state = &device->state;
struct pipe_constant_buffer cb;
DBG("vs=%p ps=%p\n", device->state.vs, device->state.ps);
/* NOTE: the only reference belongs to the hash table */
if (!device->state.vs)
if (!device->state.vs) {
device->ff.vs = nine_ff_get_vs(device);
if (!device->state.ps)
device->state.changed.group |= NINE_STATE_VS;
}
if (!device->state.ps) {
device->ff.ps = nine_ff_get_ps(device);
device->state.changed.group |= NINE_STATE_PS;
}
if (!device->state.vs) {
if (device->state.ff.clobber.vs_const) {
device->state.ff.clobber.vs_const = FALSE;
device->state.changed.group |=
NINE_STATE_FF_VSTRANSF |
NINE_STATE_FF_MATERIAL |
NINE_STATE_FF_LIGHTING |
NINE_STATE_FF_OTHER;
device->state.ff.changed.transform[0] |= 0xff000c;
device->state.ff.changed.transform[8] |= 0xff;
}
nine_ff_load_vs_transforms(device);
nine_ff_load_tex_matrices(device);
nine_ff_load_lights(device);
@ -1792,57 +1857,45 @@ nine_ff_update(struct NineDevice9 *device)
memset(state->ff.changed.transform, 0, sizeof(state->ff.changed.transform));
device->state.changed.group |= NINE_STATE_VS;
device->state.changed.group |= NINE_STATE_VS_CONST;
cb.buffer_offset = 0;
cb.buffer = NULL;
cb.user_buffer = device->ff.vs_const;
cb.buffer_size = NINE_FF_NUM_VS_CONST * 4 * sizeof(float);
if (device->prefer_user_constbuf) {
struct pipe_context *pipe = device->pipe;
struct pipe_constant_buffer cb;
cb.buffer_offset = 0;
cb.buffer = NULL;
cb.user_buffer = device->ff.vs_const;
cb.buffer_size = NINE_FF_NUM_VS_CONST * 4 * sizeof(float);
pipe->set_constant_buffer(pipe, PIPE_SHADER_VERTEX, 0, &cb);
} else {
struct pipe_box box;
u_box_1d(0, NINE_FF_NUM_VS_CONST * 4 * sizeof(float), &box);
pipe->transfer_inline_write(pipe, device->constbuf_vs, 0,
0, &box,
device->ff.vs_const, 0, 0);
nine_ranges_insert(&device->state.changed.vs_const_f, 0, NINE_FF_NUM_VS_CONST,
&device->range_pool);
if (!device->driver_caps.user_cbufs) {
u_upload_data(device->constbuf_uploader,
0,
cb.buffer_size,
cb.user_buffer,
&cb.buffer_offset,
&cb.buffer);
u_upload_unmap(device->constbuf_uploader);
cb.user_buffer = NULL;
}
state->pipe.cb_vs_ff = cb;
state->commit |= NINE_STATE_COMMIT_CONST_VS;
}
if (!device->state.ps) {
if (device->state.ff.clobber.ps_const) {
device->state.ff.clobber.ps_const = FALSE;
device->state.changed.group |=
NINE_STATE_FF_PSSTAGES |
NINE_STATE_FF_OTHER;
}
nine_ff_load_ps_params(device);
device->state.changed.group |= NINE_STATE_PS;
device->state.changed.group |= NINE_STATE_PS_CONST;
cb.buffer_offset = 0;
cb.buffer = NULL;
cb.user_buffer = device->ff.ps_const;
cb.buffer_size = NINE_FF_NUM_PS_CONST * 4 * sizeof(float);
if (device->prefer_user_constbuf) {
struct pipe_context *pipe = device->pipe;
struct pipe_constant_buffer cb;
cb.buffer_offset = 0;
cb.buffer = NULL;
cb.user_buffer = device->ff.ps_const;
cb.buffer_size = NINE_FF_NUM_PS_CONST * 4 * sizeof(float);
pipe->set_constant_buffer(pipe, PIPE_SHADER_FRAGMENT, 0, &cb);
} else {
struct pipe_box box;
u_box_1d(0, NINE_FF_NUM_PS_CONST * 4 * sizeof(float), &box);
pipe->transfer_inline_write(pipe, device->constbuf_ps, 0,
0, &box,
device->ff.ps_const, 0, 0);
nine_ranges_insert(&device->state.changed.ps_const_f, 0, NINE_FF_NUM_PS_CONST,
&device->range_pool);
if (!device->driver_caps.user_cbufs) {
u_upload_data(device->constbuf_uploader,
0,
cb.buffer_size,
cb.user_buffer,
&cb.buffer_offset,
&cb.buffer);
u_upload_unmap(device->constbuf_uploader);
cb.user_buffer = NULL;
}
state->pipe.cb_ps_ff = cb;
state->commit |= NINE_STATE_COMMIT_CONST_PS;
}
device->state.changed.group &= ~NINE_STATE_FF;

81
src/gallium/state_trackers/nine/nine_ff.h
View file

@ -3,6 +3,7 @@
#define _NINE_FF_H_
#include "device9.h"
#include "vertexdeclaration9.h"
boolean nine_ff_init(struct NineDevice9 *);
void nine_ff_fini(struct NineDevice9 *);
@ -29,4 +30,84 @@ nine_d3d_matrix_inverse_3x3(D3DMATRIX *, const D3DMATRIX *);
void
nine_d3d_matrix_transpose(D3DMATRIX *, const D3DMATRIX *);
#define NINED3DTSS_TCI_DISABLE 0
#define NINED3DTSS_TCI_PASSTHRU 1
#define NINED3DTSS_TCI_CAMERASPACENORMAL 2
#define NINED3DTSS_TCI_CAMERASPACEPOSITION 3
#define NINED3DTSS_TCI_CAMERASPACEREFLECTIONVECTOR 4
#define NINED3DTSS_TCI_SPHEREMAP 5
static inline unsigned
nine_decltype_get_dim(BYTE type)
{
switch (type) {
case D3DDECLTYPE_FLOAT1: return 1;
case D3DDECLTYPE_FLOAT2: return 2;
case D3DDECLTYPE_FLOAT3: return 3;
case D3DDECLTYPE_FLOAT4: return 4;
case D3DDECLTYPE_D3DCOLOR: return 1;
case D3DDECLTYPE_UBYTE4: return 4;
case D3DDECLTYPE_SHORT2: return 2;
case D3DDECLTYPE_SHORT4: return 4;
case D3DDECLTYPE_UBYTE4N: return 4;
case D3DDECLTYPE_SHORT2N: return 2;
case D3DDECLTYPE_SHORT4N: return 4;
case D3DDECLTYPE_USHORT2N: return 2;
case D3DDECLTYPE_USHORT4N: return 4;
case D3DDECLTYPE_UDEC3: return 3;
case D3DDECLTYPE_DEC3N: return 3;
case D3DDECLTYPE_FLOAT16_2: return 2;
case D3DDECLTYPE_FLOAT16_4: return 4;
default:
assert(!"Implementation error !");
}
return 0;
}
static inline uint16_t
nine_ff_get_projected_key(struct nine_state *state)
{
unsigned s, i;
uint16_t projected = 0;
char input_texture_coord[8];
memset(&input_texture_coord, 0, sizeof(input_texture_coord));
if (state->vdecl) {
for (i = 0; i < state->vdecl->nelems; i++) {
uint16_t usage = state->vdecl->usage_map[i];
if (usage % NINE_DECLUSAGE_COUNT == NINE_DECLUSAGE_TEXCOORD) {
s = usage / NINE_DECLUSAGE_COUNT;
if (s < 8)
input_texture_coord[s] = nine_decltype_get_dim(state->vdecl->decls[i].Type);
}
}
}
for (s = 0; s < 8; ++s) {
unsigned gen = (state->ff.tex_stage[s][D3DTSS_TEXCOORDINDEX] >> 16) + 1;
unsigned dim = state->ff.tex_stage[s][D3DTSS_TEXTURETRANSFORMFLAGS] & 0x7;
unsigned proj = !!(state->ff.tex_stage[s][D3DTSS_TEXTURETRANSFORMFLAGS] & D3DTTFF_PROJECTED);
if (!state->vs) {
if (dim > 4)
dim = input_texture_coord[s];
if (!dim && gen == NINED3DTSS_TCI_PASSTHRU)
dim = input_texture_coord[s];
else if (!dim)
dim = 4;
if (dim == 1) /* NV behaviour */
proj = 0;
if (dim > input_texture_coord[s] && gen == NINED3DTSS_TCI_PASSTHRU)
proj = 0;
} else {
dim = 4;
}
if (proj)
projected |= (dim-1) << (2 * s);
}
return projected;
}
#endif /* _NINE_FF_H_ */

42
src/gallium/state_trackers/nine/nine_pipe.c
View file

@ -27,7 +27,8 @@
#include "cso_cache/cso_context.h"
void
nine_convert_dsa_state(struct cso_context *ctx, const DWORD *rs)
nine_convert_dsa_state(struct pipe_depth_stencil_alpha_state *dsa_state,
const DWORD *rs)
{
struct pipe_depth_stencil_alpha_state dsa;
@ -65,16 +66,15 @@ nine_convert_dsa_state(struct cso_context *ctx, const DWORD *rs)
dsa.alpha.ref_value = (float)rs[D3DRS_ALPHAREF] / 255.0f;
}
cso_set_depth_stencil_alpha(ctx, &dsa);
*dsa_state = dsa;
}
/* TODO: Keep a static copy in device so we don't have to memset every time ? */
void
nine_convert_rasterizer_state(struct cso_context *ctx, const DWORD *rs)
nine_convert_rasterizer_state(struct pipe_rasterizer_state *rast_state, const DWORD *rs)
{
struct pipe_rasterizer_state rast;
memset(&rast, 0, sizeof(rast)); /* memcmp safety */
memset(&rast, 0, sizeof(rast));
rast.flatshade = rs[D3DRS_SHADEMODE] == D3DSHADE_FLAT;
/* rast.light_twoside = 0; */
@ -92,7 +92,7 @@ nine_convert_rasterizer_state(struct cso_context *ctx, const DWORD *rs)
/* rast.poly_stipple_enable = 0; */
/* rast.point_smooth = 0; */
rast.sprite_coord_mode = PIPE_SPRITE_COORD_UPPER_LEFT;
rast.point_quad_rasterization = !!rs[D3DRS_POINTSPRITEENABLE];
rast.point_quad_rasterization = 1;
rast.point_size_per_vertex = rs[NINED3DRS_VSPOINTSIZE];
rast.multisample = !!rs[D3DRS_MULTISAMPLEANTIALIAS];
rast.line_smooth = !!rs[D3DRS_ANTIALIASEDLINEENABLE];
@ -110,12 +110,28 @@ nine_convert_rasterizer_state(struct cso_context *ctx, const DWORD *rs)
/* rast.line_stipple_pattern = 0; */
rast.sprite_coord_enable = rs[D3DRS_POINTSPRITEENABLE] ? 0xff : 0x00;
rast.line_width = 1.0f;
rast.point_size = rs[NINED3DRS_VSPOINTSIZE] ? 1.0f : asfloat(rs[D3DRS_POINTSIZE]); /* XXX: D3DRS_POINTSIZE_MIN/MAX */
rast.offset_units = asfloat(rs[D3DRS_DEPTHBIAS]) * asfloat(rs[NINED3DRS_ZBIASSCALE]);
if (rs[NINED3DRS_VSPOINTSIZE]) {
rast.point_size = 1.0f;
} else {
rast.point_size = CLAMP(asfloat(rs[D3DRS_POINTSIZE]),
asfloat(rs[D3DRS_POINTSIZE_MIN]),
asfloat(rs[D3DRS_POINTSIZE_MAX]));
}
/* offset_units has the ogl/d3d11 meaning.
* d3d9: offset = scale * dz + bias
* ogl/d3d11: offset = scale * dz + r * bias
* with r implementation dependant and is supposed to be
* the smallest value the depth buffer format can hold.
* In practice on current and past hw it seems to be 2^-23
* for all formats except float formats where it varies depending
* on the content.
* For now use 1 << 23, but in the future perhaps add a way in gallium
* to get r for the format or get the gallium behaviour */
rast.offset_units = asfloat(rs[D3DRS_DEPTHBIAS]) * (float)(1 << 23);
rast.offset_scale = asfloat(rs[D3DRS_SLOPESCALEDEPTHBIAS]);
/* rast.offset_clamp = 0.0f; */
cso_set_rasterizer(ctx, &rast);
*rast_state = rast;
}
static inline void
@ -137,7 +153,7 @@ nine_convert_blend_state_fixup(struct pipe_blend_state *blend, const DWORD *rs)
}
void
nine_convert_blend_state(struct cso_context *ctx, const DWORD *rs)
nine_convert_blend_state(struct pipe_blend_state *blend_state, const DWORD *rs)
{
struct pipe_blend_state blend;
@ -181,7 +197,7 @@ nine_convert_blend_state(struct cso_context *ctx, const DWORD *rs)
/* blend.force_srgb = !!rs[D3DRS_SRGBWRITEENABLE]; */
cso_set_blend(ctx, &blend);
*blend_state = blend;
}
void
@ -239,8 +255,8 @@ nine_pipe_context_clear(struct NineDevice9 *This)
cso_set_samplers(cso, PIPE_SHADER_VERTEX, 0, NULL);
cso_set_samplers(cso, PIPE_SHADER_FRAGMENT, 0, NULL);
pipe->set_sampler_views(pipe, PIPE_SHADER_FRAGMENT, 0, 0, NULL);
pipe->set_sampler_views(pipe, PIPE_SHADER_VERTEX, 0, 0, NULL);
cso_set_sampler_views(cso, PIPE_SHADER_VERTEX, 0, NULL);
cso_set_sampler_views(cso, PIPE_SHADER_FRAGMENT, 0, NULL);
pipe->set_vertex_buffers(pipe, 0, This->caps.MaxStreams, NULL);
pipe->set_index_buffer(pipe, NULL);

67
src/gallium/state_trackers/nine/nine_pipe.h
View file

@ -27,6 +27,7 @@
#include "pipe/p_format.h"
#include "pipe/p_screen.h"
#include "pipe/p_state.h" /* pipe_box */
#include "util/macros.h"
#include "util/u_rect.h"
#include "util/u_format.h"
#include "nine_helpers.h"
@ -36,9 +37,9 @@ struct cso_context;
extern const enum pipe_format nine_d3d9_to_pipe_format_map[120];
extern const D3DFORMAT nine_pipe_to_d3d9_format_map[PIPE_FORMAT_COUNT];
void nine_convert_dsa_state(struct cso_context *, const DWORD *);
void nine_convert_rasterizer_state(struct cso_context *, const DWORD *);
void nine_convert_blend_state(struct cso_context *, const DWORD *);
void nine_convert_dsa_state(struct pipe_depth_stencil_alpha_state *, const DWORD *);
void nine_convert_rasterizer_state(struct pipe_rasterizer_state *, const DWORD *);
void nine_convert_blend_state(struct pipe_blend_state *, const DWORD *);
void nine_convert_sampler_state(struct cso_context *, int idx, const DWORD *);
void nine_pipe_context_clear(struct NineDevice9 *);
@ -81,6 +82,49 @@ rect_to_pipe_box(struct pipe_box *dst, const RECT *src)
dst->depth = 1;
}
static inline void
pipe_box_to_rect(RECT *dst, const struct pipe_box *src)
{
dst->left = src->x;
dst->right = src->x + src->width;
dst->top = src->y;
dst->bottom = src->y + src->height;
}
static inline void
rect_minify_inclusive(RECT *rect)
{
rect->left = rect->left >> 2;
rect->top = rect->top >> 2;
rect->right = DIV_ROUND_UP(rect->right, 2);
rect->bottom = DIV_ROUND_UP(rect->bottom, 2);
}
/* We suppose:
* 0 <= rect->left < rect->right
* 0 <= rect->top < rect->bottom
*/
static inline void
fit_rect_format_inclusive(enum pipe_format format, RECT *rect, int width, int height)
{
const unsigned w = util_format_get_blockwidth(format);
const unsigned h = util_format_get_blockheight(format);
if (util_format_is_compressed(format)) {
rect->left = rect->left - rect->left % w;
rect->top = rect->top - rect->top % h;
rect->right = (rect->right % w) == 0 ?
rect->right :
rect->right - (rect->right % w) + w;
rect->bottom = (rect->bottom % h) == 0 ?
rect->bottom :
rect->bottom - (rect->bottom % h) + h;
}
rect->right = MIN2(rect->right, width);
rect->bottom = MIN2(rect->bottom, height);
}
static inline boolean
rect_to_pipe_box_clamp(struct pipe_box *dst, const RECT *src)
{
@ -164,6 +208,23 @@ pipe_to_d3d9_format(enum pipe_format format)
return nine_pipe_to_d3d9_format_map[format];
}
/* ATI1 and ATI2 are not officially compressed in d3d9 */
static inline boolean
compressed_format( D3DFORMAT fmt )
{
switch (fmt) {
case D3DFMT_DXT1:
case D3DFMT_DXT2:
case D3DFMT_DXT3:
case D3DFMT_DXT4:
case D3DFMT_DXT5:
return TRUE;
default:
break;
}
return FALSE;
}
static inline boolean
depth_stencil_format( D3DFORMAT fmt )
{

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